X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=intel%2Fintel_decode.c;h=a5d6e04a7e682240a85e23149eed347ff861aa8a;hb=6281cf1b4310ff0b7670677cb4113a89ebf0b619;hp=cf5b3bbe702c95113cecb49dadec4580deccad7b;hpb=eeedb0dcc48e02727606d416c28bcb9b86915daa;p=platform%2Fupstream%2Flibdrm.git diff --git a/intel/intel_decode.c b/intel/intel_decode.c index cf5b3bb..a5d6e04 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -21,6 +21,10 @@ * IN THE SOFTWARE. */ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + #include #include #include @@ -29,6 +33,8 @@ #include #include +#include "libdrm.h" +#include "xf86drm.h" #include "intel_chipset.h" #include "intel_bufmgr.h" @@ -104,11 +110,7 @@ static float int_as_float(uint32_t intval) return uval.f; } -static void -instr_out(struct drm_intel_decode *ctx, unsigned int index, - const char *fmt, ...) __attribute__((format(__printf__, 3, 4))); - -static void +static void DRM_PRINTFLIKE(3, 4) instr_out(struct drm_intel_decode *ctx, unsigned int index, const char *fmt, ...) { @@ -139,6 +141,22 @@ instr_out(struct drm_intel_decode *ctx, unsigned int index, } static int +decode_MI_SET_CONTEXT(struct drm_intel_decode *ctx) +{ + uint32_t data = ctx->data[1]; + if (ctx->gen > 7) + return 1; + + instr_out(ctx, 0, "MI_SET_CONTEXT\n"); + instr_out(ctx, 1, "gtt offset = 0x%x%s%s\n", + data & ~0xfff, + data & (1<<1)? ", Force Restore": "", + data & (1<<0)? ", Restore Inhibit": ""); + + return 2; +} + +static int decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx) { const char *cc_wait; @@ -233,7 +251,7 @@ decode_mi(struct drm_intel_decode *ctx) { 0x00, 0, 1, 1, "MI_NOOP" }, { 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" }, { 0x07, 0, 1, 1, "MI_REPORT_HEAD" }, - { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" }, + { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT", decode_MI_SET_CONTEXT }, { 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" }, { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" }, { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" }, @@ -241,6 +259,8 @@ decode_mi(struct drm_intel_decode *ctx) { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT }, { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" }, { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" }, + { 0x28, 0x3f, 3, 3, "MI_REPORT_PERF_COUNT" }, + { 0x29, 0xff, 3, 3, "MI_LOAD_REGISTER_MEM" }, { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"}, }, *opcode_mi = NULL; @@ -1698,7 +1718,7 @@ decode_3d_1d(struct drm_intel_decode *ctx) } } else { instr_out(ctx, i, - "S%d: 0x%08x\n", i, data[i]); + "S%d: 0x%08x\n", word, data[i]); } i++; } @@ -3146,7 +3166,7 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x7805, 0x00ff, 3, 3, "3DSTATE_URB" }, { 0x7804, 0x00ff, 3, 3, "3DSTATE_CLEAR_PARAMS" }, { 0x7806, 0x00ff, 3, 3, "3DSTATE_STENCIL_BUFFER" }, - { 0x7807, 0x00ff, 4, 4, "3DSTATE_HIER_DEPTH_BUFFER", 6 }, + { 0x790f, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 6 }, { 0x7807, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 7, gen7_3DSTATE_HIER_DEPTH_BUFFER }, { 0x7808, 0x00ff, 5, 257, "3DSTATE_VERTEX_BUFFERS" }, { 0x7809, 0x00ff, 3, 256, "3DSTATE_VERTEX_ELEMENTS" }, @@ -3208,7 +3228,7 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x790b, 0xffff, 4, 4, "3DSTATE_GS_SVB_INDEX" }, { 0x790d, 0xffff, 3, 3, "3DSTATE_MULTISAMPLE", 6 }, { 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 }, - { 0x7910, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" }, + { 0x7910, 0x00ff, 2, 2, "3DSTATE_CLEAR_PARAMS" }, { 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" }, { 0x7913, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_HS" }, { 0x7914, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_DS" }, @@ -3390,8 +3410,8 @@ decode_3d_965(struct drm_intel_decode *ctx) instr_out(ctx, i, "buffer %d: %svalid, type 0x%04x, " "src offset 0x%04x bytes\n", - data[i] >> (IS_GEN6(devid) ? 26 : 27), - data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ? + data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27), + data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ? "" : "in", (data[i] >> 16) & 0x1ff, data[i] & 0x07ff); i++; @@ -3797,7 +3817,7 @@ decode_3d_i830(struct drm_intel_decode *ctx) return 1; } -struct drm_intel_decode * +drm_public struct drm_intel_decode * drm_intel_decode_context_alloc(uint32_t devid) { struct drm_intel_decode *ctx; @@ -3809,7 +3829,9 @@ drm_intel_decode_context_alloc(uint32_t devid) ctx->devid = devid; ctx->out = stdout; - if (IS_GEN7(devid)) + if (IS_GEN8(devid)) + ctx->gen = 8; + else if (IS_GEN7(devid)) ctx->gen = 7; else if (IS_GEN6(devid)) ctx->gen = 6; @@ -3827,20 +3849,20 @@ drm_intel_decode_context_alloc(uint32_t devid) return ctx; } -void +drm_public void drm_intel_decode_context_free(struct drm_intel_decode *ctx) { free(ctx); } -void +drm_public void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx, int dump_past_end) { ctx->dump_past_end = !!dump_past_end; } -void +drm_public void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx, void *data, uint32_t hw_offset, int count) { @@ -3849,7 +3871,7 @@ drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx, ctx->base_count = count; } -void +drm_public void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, uint32_t head, uint32_t tail) { @@ -3857,7 +3879,7 @@ drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, ctx->tail = tail; } -void +drm_public void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out) { @@ -3871,7 +3893,7 @@ drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, * \param count number of DWORDs to decode in the batch buffer * \param hw_offset hardware address for the buffer */ -void +drm_public void drm_intel_decode(struct drm_intel_decode *ctx) { int ret;