X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fzynqmppl.h;h=acf75a8f079ce359f1c164cc1dff9344726961d2;hb=a29491ade0adf3dbb9dc51be8b45530edde1f1df;hp=fb5200ec84a615db9d791e59381e8d4f3062b673;hpb=0cba6abbba5c0bd5c80e652c35d0bd74e644a49e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index fb5200e..acf75a8 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -1,30 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * (C) Copyright 2015 Xilinx, Inc,
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _ZYNQMPPL_H_
 #define _ZYNQMPPL_H_
 
 #include <xilinx.h>
+#include <linux/bitops.h>
 
-#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
-#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
 #define ZYNQMP_FPGA_OP_INIT			(1 << 0)
 #define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
 #define ZYNQMP_FPGA_OP_DONE			(1 << 2)
 
+#define ZYNQMP_FPGA_FLAG_AUTHENTICATED		BIT(2)
+#define ZYNQMP_FPGA_FLAG_ENCRYPTED		BIT(3)
+
 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xf << \
 					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT	12
-#define ZYNQMP_CSU_IDCODE_SVD_MASK	(0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
+#define ZYNQMP_CSU_IDCODE_SVD_MASK	(0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
 
 extern struct xilinx_fpga_op zynqmp_op;
 
-#define XILINX_ZYNQMP_DESC \
-{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
+#define ZYNQMP_FPGA_FLAGS	(FPGA_LEGACY | \
+				 FPGA_XILINX_ZYNQMP_DDRAUTH | \
+				 FPGA_XILINX_ZYNQMP_ENC)
+#else
+#define ZYNQMP_FPGA_FLAGS	(FPGA_LEGACY)
+#endif
 
 #endif /* _ZYNQMPPL_H_ */