X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fzynqmppl.h;h=5214db99fba769b2ae8dbeba111cefacc7f2cced;hb=cc1e98b559e46630c3421a7762d02a58e5480926;hp=542ace9a03b9b6d9262bc64b0191c758e28cb500;hpb=201c9d884dcadb4e76981c30e9915f73de2d09b5;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 542ace9..5214db9 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * (C) Copyright 2015 Xilinx, Inc,
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _ZYNQMPPL_H_
@@ -12,10 +11,20 @@
 
 #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
+#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS		0xC2000017
 #define ZYNQMP_FPGA_OP_INIT			(1 << 0)
 #define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
 #define ZYNQMP_FPGA_OP_DONE			(1 << 2)
 
+#define ZYNQMP_FPGA_FLAG_AUTHENTICATED		BIT(2)
+#define ZYNQMP_FPGA_FLAG_ENCRYPTED		BIT(3)
+
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xf << \
+					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
+#define ZYNQMP_CSU_IDCODE_SVD_SHIFT	12
+#define ZYNQMP_CSU_IDCODE_SVD_MASK	(0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
+
 extern struct xilinx_fpga_op zynqmp_op;
 
 #define XILINX_ZYNQMP_DESC \