X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fusb%2Fehci-fsl.h;h=e9349b5c1666db1838ef8da34d194ee5c83bbb16;hb=68d534201733e84257e357f7ddcb379dbe1cc5d0;hp=9e106fc42295d74c3332ba9752391f649cbbf9d3;hpb=326ea986ac150acdc7656d57fca647db80b50158;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 9e106fc..e9349b5 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -11,6 +11,8 @@
 
 #include <asm/processor.h>
 
+#define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */
+
 /* Global offsets */
 #define FSL_SKIP_PCI		0x100
 
@@ -149,14 +151,31 @@
 #define MPC83XX_SCCR_USB_DRCM_10	0x00200000
 
 #if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
+#if defined(CONFIG_MPC834x)
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
+#else
+#define CONFIG_SYS_FSL_USB2_ADDR	0
+#endif
 #elif defined(CONFIG_MPC85xx)
-#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
 #elif defined(CONFIG_MPC512X)
-#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR	0
+#elif defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
 
 /*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH		4
+
+/*
  * USB Registers
  */
 struct usb_ehci {
@@ -261,7 +280,9 @@ struct usb_ehci {
 #define MXC_EHCI_IPPUE_DOWN		(1 << 10)
 #define MXC_EHCI_IPPUE_UP		(1 << 11)
 
+int usb_phy_mode(int port);
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
+int board_usb_phy_mode(int port);
 
 #endif /* _EHCI_FSL_H */