X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fppc4xx_enet.h;h=3e10883f984ab8bcdea241a3a80b493d50308c15;hb=84efbf4d144ff8aaed3cca036aebb1fe69eff3f4;hp=89ff26f991254b4863d4905ecf48524ccaa9e644;hpb=e59af4b611408adcdfb5e19bc5194a7d1f8b4dc3;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 89ff26f..3e10883 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -153,13 +153,27 @@ typedef struct emac_4xx_hw_st {
 #define SDR0_PFC1_EM_1000	(0x00200000)
 #endif
 
+/*
+ * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
+ * not have a pin function control (PFC) register to otherwise determine
+ * the bridge configuration.
+ */
+#define EMAC_PHY_MODE_NONE		0
+#define EMAC_PHY_MODE_NONE_RGMII	1
+#define EMAC_PHY_MODE_RGMII_NONE	2
+#define EMAC_PHY_MODE_RGMII_RGMII	3
+#define EMAC_PHY_MODE_NONE_GMII		4
+#define EMAC_PHY_MODE_GMII_NONE		5
+#define EMAC_PHY_MODE_NONE_MII		6
+#define EMAC_PHY_MODE_MII_NONE		7
+
 /* ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0D00)
+#define ZMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
 #else
-#define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
 #endif
 #define ZMII_FER		(ZMII_BASE)
 #define ZMII_SSR		(ZMII_BASE + 4)
@@ -202,13 +216,13 @@ typedef struct emac_4xx_hw_st {
 
 /* RGMII Register Addresses */
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1000)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1500)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
 #elif defined(CONFIG_405EX)
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0xB00)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
 #else
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
 #endif
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)
@@ -218,12 +232,12 @@ typedef struct emac_4xx_hw_st {
 #endif
 
 /* RGMII Function Enable (FER) Register Bit Definitions */
-/* Note: for EMAC 2 and 3 only, 440GX only */
 #define RGMII_FER_DIS		(0x00)
 #define RGMII_FER_RTBI		(0x04)
 #define RGMII_FER_RGMII		(0x05)
 #define RGMII_FER_TBI		(0x06)
 #define RGMII_FER_GMII		(0x07)
+#define RGMII_FER_MII		(RGMII_FER_GMII)
 
 #define RGMII_FER_V(__x)	((__x - 2) * 4)
 
@@ -246,7 +260,7 @@ typedef struct emac_4xx_hw_st {
 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 +---------------------------------------------------------------------------*/
 #if defined(CONFIG_440GX)
-#define TAH_BASE		(CFG_PERIPHERAL_BASE + 0x0B50)
+#define TAH_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
 #define TAH_REVID		(TAH_BASE + 0x0)    /* Revision ID (RO)*/
 #define TAH_MR			(TAH_BASE + 0x10)   /* Mode Register (R/W) */
 #define TAH_SSR0		(TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
@@ -312,15 +326,15 @@ typedef struct emac_4xx_hw_st {
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0E00)
+#define EMAC_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
 #else
-#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0800)
+#define EMAC_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
 #endif
 #else
 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC_BASE 		0xEF600900
+#define EMAC_BASE		0xEF600900
 #else
-#define EMAC_BASE 		0xEF600800
+#define EMAC_BASE		0xEF600800
 #endif
 #endif
 
@@ -362,6 +376,7 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M1_APP		(0x08000000)
 #define EMAC_M1_RSVD		(0x06000000)
 #define EMAC_M1_IST		(0x01000000)
+#define EMAC_M1_MF_1000GPCS	(0x00C00000)
 #define EMAC_M1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
 #define EMAC_M1_MF_100MBPS	(0x00400000)
 #define EMAC_M1_RFS_MASK	(0x00380000)
@@ -380,6 +395,8 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M1_MWSW		(0x00007000)
 #define EMAC_M1_JUMBO_ENABLE	(0x00000800)
 #define EMAC_M1_IPPA		(0x000007c0)
+#define EMAC_M1_IPPA_SET(id)	(((id) & 0x1f) << 6)
+#define EMAC_M1_IPPA_GET(id)	(((id) >> 6) & 0x1f)
 #define EMAC_M1_OBCI_GT100	(0x00000020)
 #define EMAC_M1_OBCI_100	(0x00000018)
 #define EMAC_M1_OBCI_83		(0x00000010)