X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fppc4xx.h;h=f1478854d116e30f9d69789b15da56dd1bb807d9;hb=3405f38a15eec5092ac47efe0829f10a24491c6e;hp=59a3b06b71cdc300f171c48802ac0cd66af2b690;hpb=afe3848b79a7ff351e9fbf3a7c162d2de002279b;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 59a3b06..f147885 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -107,8 +107,8 @@
  * Enable long long (%ll ...) printf format on 440 PPC's since most of
  * them support 36bit physical addressing
  */
-#define CFG_64BIT_VSPRINTF
-#define CFG_64BIT_STRTOUL
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
 #include <ppc440.h>
 #else
 #include <ppc405.h>
@@ -143,7 +143,7 @@
 #define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
 
 #define RESET_VECTOR	0xfffffffc
-#define CACHELINE_MASK	(CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+#define CACHELINE_MASK	(CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
 						     line aligned data. */
 
 #define CPR0_DCR_BASE	0x0C
@@ -203,6 +203,22 @@ typedef struct
 	unsigned long pllPlbDiv;
 } PPC4xx_SYS_INFO;
 
+static inline u32 get_mcsr(void)
+{
+	u32 val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
 #endif	/* __ASSEMBLY__ */
 
+/* for multi-cpu support */
+#define NA_OR_UNKNOWN_CPU	-1
+
 #endif	/* __PPC4XX_H__ */