X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fpci.h;h=eebe8a8a548c4785c6361f3ebe80afa72d43fdce;hb=5df70e91c72dab45b7d81e4568b12e5a5b5f90ec;hp=e0e8783a7aa1f85b41aa1d9866aa994dc5dac9c4;hpb=41ec8b1803804b7e0644d07af4977c339a575b80;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/pci.h b/include/pci.h
index e0e8783..eebe8a8 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -101,8 +101,8 @@
 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
 #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
 #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
-#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
+#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
+#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
 /* bit 1 is reserved if address_space = 1 */
 
 /* Header type 0 (normal devices) */
@@ -111,7 +111,7 @@
 #define PCI_SUBSYSTEM_ID	0x2e
 #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
+#define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
 
 #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
 
@@ -302,17 +302,31 @@
 #define PCI_MAX_PCI_DEVICES	32
 #define PCI_MAX_PCI_FUNCTIONS	8
 
+#define PCI_DCR		0x54    /* PCIe Device Control Register */
+#define PCI_DSR		0x56    /* PCIe Device Status Register */
+#define PCI_LSR		0x5e    /* PCIe Link Status Register */
+#define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
+#define  PCI_LTSSM_L0	0x16    /* L0 state */
+
 /* Include the ID list */
 
 #include <pci_ids.h>
 
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
 struct pci_region {
-	unsigned long bus_start;		/* Start on the bus */
-	unsigned long phys_start;		/* Start in physical address space */
-	unsigned long size;			/* Size */
-	unsigned long flags;			/* Resource flags */
+	pci_addr_t bus_start;	/* Start on the bus */
+	phys_addr_t phys_start;	/* Start in physical address space */
+	pci_size_t size;	/* Size */
+	unsigned long flags;	/* Resource flags */
 
-	unsigned long bus_lower;
+	pci_addr_t bus_lower;
 };
 
 #define PCI_REGION_MEM		0x00000000	/* PCI memory space */
@@ -324,9 +338,9 @@ struct pci_region {
 #define PCI_REGION_RO		0x00000200	/* Read-only memory */
 
 extern __inline__ void pci_set_region(struct pci_region *reg,
-				      unsigned long bus_start,
-				      unsigned long phys_start,
-				      unsigned long size,
+				      pci_addr_t bus_start,
+				      phys_addr_t phys_start,
+				      pci_size_t size,
 				      unsigned long flags) {
 	reg->bus_start	= bus_start;
 	reg->phys_start = phys_start;
@@ -426,10 +440,10 @@ extern __inline__ void pci_set_ops(struct pci_controller *hose,
 
 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
 
-extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
-					  unsigned long addr, unsigned long flags);
-extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
-					  unsigned long addr, unsigned long flags);
+extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+					pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+					phys_addr_t addr, unsigned long flags);
 
 #define pci_phys_to_bus(dev, addr, flags) \
 	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
@@ -477,8 +491,8 @@ extern int pci_hose_scan(struct pci_controller *hose);
 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
 
 extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, unsigned long size);
-extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
+extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
 extern void pciauto_setup_device(struct pci_controller *hose,
 				 pci_dev_t dev, int bars_num,
 				 struct pci_region *mem,
@@ -494,11 +508,14 @@ extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
 extern int pci_hose_config_device(struct pci_controller *hose,
 				  pci_dev_t dev,
 				  unsigned long io,
-				  unsigned long mem,
+				  pci_addr_t mem,
 				  unsigned long command);
 
 #ifdef CONFIG_MPC824X
 extern void pci_mpc824x_init (struct pci_controller *hose);
 #endif
 
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
 #endif	/* _PCI_H */