X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fpci.h;h=c55d6107a49af6d7897f564007a6ff53541cafe5;hb=6786ce1ce14feb4d02854a0c04bc0cce505be46e;hp=d1ccf6c9636fae240b7f7693f718452f052a1104;hpb=2c31d7e746766f47a007f39c030706e493a9cc77;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/pci.h b/include/pci.h index d1ccf6c..c55d610 100644 --- a/include/pci.h +++ b/include/pci.h @@ -5,6 +5,7 @@ * * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Copyright (c) 2021 Maciej W. Rozycki */ #ifndef _PCI_H @@ -54,130 +55,7 @@ #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ #define PCI_CLASS_CODE 0x0b /* Device class code */ -#define PCI_CLASS_CODE_TOO_OLD 0x00 -#define PCI_CLASS_CODE_STORAGE 0x01 -#define PCI_CLASS_CODE_NETWORK 0x02 -#define PCI_CLASS_CODE_DISPLAY 0x03 -#define PCI_CLASS_CODE_MULTIMEDIA 0x04 -#define PCI_CLASS_CODE_MEMORY 0x05 -#define PCI_CLASS_CODE_BRIDGE 0x06 -#define PCI_CLASS_CODE_COMM 0x07 -#define PCI_CLASS_CODE_PERIPHERAL 0x08 -#define PCI_CLASS_CODE_INPUT 0x09 -#define PCI_CLASS_CODE_DOCKING 0x0A -#define PCI_CLASS_CODE_PROCESSOR 0x0B -#define PCI_CLASS_CODE_SERIAL 0x0C -#define PCI_CLASS_CODE_WIRELESS 0x0D -#define PCI_CLASS_CODE_I2O 0x0E -#define PCI_CLASS_CODE_SATELLITE 0x0F -#define PCI_CLASS_CODE_CRYPTO 0x10 -#define PCI_CLASS_CODE_DATA 0x11 -/* Base Class 0x12 - 0xFE is reserved */ -#define PCI_CLASS_CODE_OTHER 0xFF - #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ -#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 -#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 -#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 -#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 -#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 -#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 -#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 -#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 -#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 -#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 -#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 -#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 -#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 -#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 -#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 -#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 -#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 -#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 -#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 -#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 -#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 -#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 -#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 -#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 -#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 -#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 -#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 -#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 -#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 -#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 -#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 -#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 -#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 -#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 -#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 -#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A -#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 -#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 -#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 -#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 -#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 -#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 -#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 -#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 -#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 -#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 -#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 -#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 -#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 -#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 -#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 -#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 -#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 -#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 -#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 -#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 -#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 -#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 -#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 -#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 -#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 -#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 -#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 -#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 -#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 -#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 -#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 -#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 -#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 -#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 -#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 -#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 -#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 -#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 -#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 -#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 -#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 -#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 -#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 -#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 -#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 -#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 -#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 -#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 -#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 -#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ @@ -475,16 +353,40 @@ /* PCI Express capabilities */ #define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_VERS 0x000f /* Capability Version */ #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */ +#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ +#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ +#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ +#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ +#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ #define PCI_EXP_LNKSTA 18 /* Link Status */ #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ @@ -492,15 +394,35 @@ #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ +#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_RTCTL 28 /* Root Control */ +#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ +#define PCI_EXP_RTCAP 30 /* Root Capabilities */ +#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ - +#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ +#define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +#define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */ +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Target Link Speed 2.5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */ +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */ + +/* Advanced Error Reporting */ +#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ +#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ +#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ +#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ +#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ +#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ + /* Single Root I/O Virtualization Registers */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ @@ -518,6 +440,77 @@ #include +/* + * Config Address for PCI Configuration Mechanism #1 + * + * See PCI Local Bus Specification, Revision 3.0, + * Section 3.2.2.3.2, Figure 3-2, p. 50. + */ + +#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ +#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ +#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ + +#define PCI_CONF1_BUS_MASK 0xff +#define PCI_CONF1_DEV_MASK 0x1f +#define PCI_CONF1_FUNC_MASK 0x7 +#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ + +#define PCI_CONF1_ENABLE BIT(31) +#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) +#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) +#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) +#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) + +#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ENABLE | \ + PCI_CONF1_BUS(bus) | \ + PCI_CONF1_DEV(dev) | \ + PCI_CONF1_FUNC(func) | \ + PCI_CONF1_REG(reg)) + +/* + * Extension of PCI Config Address for accessing extended PCIe registers + * + * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs + * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address + * are used for specifying additional 4 high bits of PCI Express register. + */ + +#define PCI_CONF1_EXT_REG_SHIFT 16 +#define PCI_CONF1_EXT_REG_MASK 0xf00 +#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) + +#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ + PCI_CONF1_EXT_REG(reg)) + +/* + * Enhanced Configuration Access Mechanism (ECAM) + * + * See PCI Express Base Specification, Revision 5.0, Version 1.0, + * Section 7.2.2, Table 7-1, p. 677. + */ +#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ +#define PCIE_ECAM_DEV_SHIFT 15 /* Device number */ +#define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */ + +#define PCIE_ECAM_BUS_MASK 0xff +#define PCIE_ECAM_DEV_MASK 0x1f +#define PCIE_ECAM_FUNC_MASK 0x7 +#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ + +#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) +#define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT) +#define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT) +#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) + +#define PCIE_ECAM_OFFSET(bus, dev, func, where) \ + (PCIE_ECAM_BUS(bus) | \ + PCIE_ECAM_DEV(dev) | \ + PCIE_ECAM_FUNC(func) | \ + PCIE_ECAM_REG(where)) + #ifndef __ASSEMBLY__ #include @@ -578,7 +571,6 @@ typedef int pci_dev_t; #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) -#define PCI_VENDEV(v, d) (((v) << 16) | (d)) #define PCI_ANY_ID (~0) /* Convert from Linux format to U-Boot format */ @@ -624,13 +616,9 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev * about a small subset of PCI devices. This is normally false. */ struct pci_controller { -#ifdef CONFIG_DM_PCI struct udevice *bus; struct udevice *ctlr; bool skip_auto_config_until_reloc; -#else - struct pci_controller *next; -#endif int first_busno; int last_busno; @@ -656,54 +644,12 @@ struct pci_controller { struct pci_config_table *config_table; void (*fixup_irq)(struct pci_controller *, pci_dev_t); -#ifndef CONFIG_DM_PCI - /* Low-level architecture-dependent routines */ - int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); - int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); - int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); - int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); - int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); - int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); -#endif /* Used by auto config */ struct pci_region *pci_mem, *pci_io, *pci_prefetch; - -#ifndef CONFIG_DM_PCI - int current_busno; - - void *priv_data; -#endif }; -#ifndef CONFIG_DM_PCI -static inline void pci_set_ops(struct pci_controller *hose, - int (*read_byte)(struct pci_controller*, - pci_dev_t, int where, u8 *), - int (*read_word)(struct pci_controller*, - pci_dev_t, int where, u16 *), - int (*read_dword)(struct pci_controller*, - pci_dev_t, int where, u32 *), - int (*write_byte)(struct pci_controller*, - pci_dev_t, int where, u8), - int (*write_word)(struct pci_controller*, - pci_dev_t, int where, u16), - int (*write_dword)(struct pci_controller*, - pci_dev_t, int where, u32)) { - hose->read_byte = read_byte; - hose->read_word = read_word; - hose->read_dword = read_dword; - hose->write_byte = write_byte; - hose->write_word = write_word; - hose->write_dword = write_dword; -} -#endif - -#ifdef CONFIG_PCI_INDIRECT_BRIDGE -extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); -#endif - -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) +#if defined(CONFIG_DM_PCI_COMPAT) extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, pci_addr_t addr, unsigned long flags); extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, @@ -753,15 +699,6 @@ extern int pci_hose_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 val); #endif -#ifndef CONFIG_DM_PCI -extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); -extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); -extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); -extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); -extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); -extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); -#endif - void pciauto_region_init(struct pci_region *res); void pciauto_region_align(struct pci_region *res, pci_size_t size); void pciauto_config_init(struct pci_controller *hose); @@ -776,12 +713,13 @@ void pciauto_config_init(struct pci_controller *hose); * @size: Amount of bytes to allocate * @bar: Returns the PCI bus address of the allocated resource * @supports_64bit: Whether to allow allocations above the 32-bit boundary - * @return 0 if successful, -1 on failure + * Return: 0 if successful, -1 on failure */ int pciauto_region_allocate(struct pci_region *res, pci_size_t size, pci_addr_t *bar, bool supports_64bit); +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) +#if defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, @@ -797,7 +735,6 @@ extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern struct pci_controller *pci_get_hose_head(void); -extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); @@ -828,13 +765,7 @@ int pci_find_next_ext_capability(struct pci_controller *hose, int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, int cap); -#ifdef CONFIG_PCI_FIXUP_DEV -extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, - unsigned short vendor, - unsigned short device, - unsigned short class); -#endif -#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ +#endif /* defined(CONFIG_DM_PCI_COMPAT) */ const char * pci_class_str(u8 class); int pci_last_busno(void); @@ -843,11 +774,6 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif -#ifdef CONFIG_PCIE_IMX -extern void imx_pcie_remove(void); -#endif - -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits * @@ -855,6 +781,8 @@ extern void imx_pcie_remove(void); * with devices which require hard-coded addresses, not part of the normal * PCI enumeration process. * + * This is only available if CONFIG_DM_PCI_COMPAT is enabled + * * @hose: PCI hose to use * @dev: PCI device to update * @barnum: BAR number (0-5) @@ -866,16 +794,20 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, /** * pci_read_bar32() - read the address of a bar * + * This is only available if CONFIG_DM_PCI_COMPAT is enabled + * * @hose: PCI hose to use * @dev: PCI device to inspect * @barnum: BAR number (0-5) - * @return address of the bar, masking out any control bits + * Return: address of the bar, masking out any control bits * */ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); /** * pci_hose_find_devices() - Find devices by vendor/device ID * + * This is only available if CONFIG_DM_PCI_COMPAT is enabled + * * @hose: PCI hose to search * @busnum: Bus number to search * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record @@ -886,7 +818,6 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); */ pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, struct pci_device_id *ids, int *indexp); -#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ /* Access sizes for PCI reads and writes */ enum pci_size_t { @@ -897,13 +828,12 @@ enum pci_size_t { struct udevice; -#ifdef CONFIG_DM_PCI /** - * struct pci_child_platdata - information stored about each PCI device + * struct pci_child_plat - information stored about each PCI device * * Every device on a PCI bus has this per-child data. * - * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a + * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a * PCI bus (i.e. UCLASS_PCI) * * @devfn: Encoded device and function index - see PCI_DEVFN() @@ -914,7 +844,7 @@ struct udevice; * @pfdev: Handle to Physical Function device * @virtid: Virtual Function Index */ -struct pci_child_platdata { +struct pci_child_plat { int devfn; unsigned short vendor; unsigned short device; @@ -934,7 +864,7 @@ struct dm_pci_ops { * PCI buses must support reading and writing configuration values * so that the bus can be scanned and its devices configured. * - * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. + * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always. * If bridges exist it is possible to use the top-level bus to * access a sub-bus. In that case @bus will be the top-level bus * and PCI_BUS(bdf) will be a different (higher) value @@ -969,7 +899,7 @@ struct dm_pci_ops { * dm_pci_get_bdf() - Get the BDF value for a device * * @dev: Device to check - * @return bus/device/function value (see PCI_BDF()) + * Return: bus/device/function value (see PCI_BDF()) */ pci_dev_t dm_pci_get_bdf(const struct udevice *dev); @@ -986,7 +916,7 @@ pci_dev_t dm_pci_get_bdf(const struct udevice *dev); * driver interface. * * @bus: Bus containing devices to bind - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int pci_bind_bus_devices(struct udevice *bus); @@ -1001,7 +931,7 @@ int pci_bind_bus_devices(struct udevice *bus); * devices are mapped into memory and I/O space ready for use. * * @bus: Bus containing devices to bind - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int pci_auto_config_devices(struct udevice *bus); @@ -1010,7 +940,7 @@ int pci_auto_config_devices(struct udevice *bus); * * @bdf: PCI device address: bus, device and function -see PCI_BDF() * @devp: Returns the device for this address, if found - * @return 0 if OK, -ENODEV if not found + * Return: 0 if OK, -ENODEV if not found */ int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); @@ -1019,7 +949,7 @@ int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); * * @find_devfn: PCI device address (device and function only) * @devp: Returns the device for this address, if found - * @return 0 if OK, -ENODEV if not found + * Return: 0 if OK, -ENODEV if not found */ int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn, struct udevice **devp); @@ -1027,13 +957,13 @@ int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn, /** * pci_find_first_device() - return the first available PCI device * - * This function and pci_find_first_device() allow iteration through all + * This function and pci_find_next_device() allow iteration through all * available PCI devices on all buses. Assuming there are any, this will * return the first one. * * @devp: Set to the first available device, or NULL if no more are left * or we got an error - * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) + * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) */ int pci_find_first_device(struct udevice **devp); @@ -1045,7 +975,7 @@ int pci_find_first_device(struct udevice **devp); * * @devp: On entry, the last device returned. Set to the next available * device, or NULL if no more are left or we got an error - * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) + * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) */ int pci_find_next_device(struct udevice **devp); @@ -1053,7 +983,7 @@ int pci_find_next_device(struct udevice **devp); * pci_get_ff() - Returns a mask for the given access size * * @size: Access size - * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for + * Return: 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for * PCI_SIZE_32 */ int pci_get_ff(enum pci_size_t size); @@ -1068,9 +998,9 @@ int pci_get_ff(enum pci_size_t size); * parameter is decremented for each non-matching device so * can be called repeatedly. * @devp: Returns matching device if found - * @return 0 if found, -ENODEV if not + * Return: 0 if found, -ENODEV if not */ -int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, +int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids, int *indexp, struct udevice **devp); /** @@ -1080,9 +1010,9 @@ int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, * @index: Index number of device to find, 0 for the first match, 1 for * the second, etc. * @devp: Returns matching device if found - * @return 0 if found, -ENODEV if not + * Return: 0 if found, -ENODEV if not */ -int pci_find_device_id(struct pci_device_id *ids, int index, +int pci_find_device_id(const struct pci_device_id *ids, int index, struct udevice **devp); /** @@ -1097,7 +1027,7 @@ int pci_find_device_id(struct pci_device_id *ids, int index, * * @hose: PCI hose to scan * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int dm_pci_hose_probe_bus(struct udevice *bus); @@ -1112,7 +1042,7 @@ int dm_pci_hose_probe_bus(struct udevice *bus); * @offset: Register offset to read * @valuep: Place to put the returned value * @size: Access size - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, unsigned long *valuep, enum pci_size_t size); @@ -1125,7 +1055,7 @@ int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, * @offset: Register offset to write * @value: Value to write * @size: Access size - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, unsigned long value, enum pci_size_t size); @@ -1140,7 +1070,7 @@ int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, * @offset: Register offset to update * @clr: Bits to clear * @set: Bits to set - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, u32 clr, u32 set); @@ -1242,7 +1172,7 @@ int pci_generic_mmap_read_config( * * @pdev: Physical Function udevice handle * @vf_en: Number of Virtual Function devices to enable - * @return 0 on success, -ve on error + * Return: 0 on success, -ve on error */ int pci_sriov_init(struct udevice *pdev, int vf_en); @@ -1250,7 +1180,7 @@ int pci_sriov_init(struct udevice *pdev, int vf_en); * pci_sriov_get_totalvfs() - Get total available Virtual Function devices * * @pdev: Physical Function udevice handle - * @return count on success, -ve on error + * Return: count on success, -ve on error */ int pci_sriov_get_totalvfs(struct udevice *pdev); #endif @@ -1306,7 +1236,7 @@ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, * devices are mapped into memory and I/O space ready for use. * * @dev: Device to configure - * @return 0 if OK, -ve on error + * Return: 0 if OK, -ve on error */ int dm_pciauto_config_device(struct udevice *dev); @@ -1320,7 +1250,7 @@ int dm_pciauto_config_device(struct udevice *dev); * @value: Value to transform (32-bit value read from @offset & ~3) * @offset: Register offset that was read * @size: Required size of the result - * @return the value that would have been obtained if the read had been + * Return: the value that would have been obtained if the read had been * performed at the given offset with the correct size */ ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); @@ -1336,7 +1266,7 @@ ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); * @value: Value to transform (32-bit value read from @offset & ~3) * @offset: Register offset that should be written * @size: Required size of the write - * @return the value that should be written as a 32-bit access to @offset & ~3. + * Return: the value that should be written as a 32-bit access to @offset & ~3. */ ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, enum pci_size_t size); @@ -1345,7 +1275,7 @@ ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, * pci_get_controller() - obtain the controller to use for a bus * * @dev: Device to check - * @return pointer to the controller device for this bus + * Return: pointer to the controller device for this bus */ struct udevice *pci_get_controller(struct udevice *dev); @@ -1356,7 +1286,7 @@ struct udevice *pci_get_controller(struct udevice *dev); * @iop: Returns a pointer to the I/O region, or NULL if none * @memp: Returns a pointer to the memory region, or NULL if none * @prefp: Returns a pointer to the pre-fetch region, or NULL if none - * @return the number of non-NULL regions returned, normally 3 + * Return: the number of non-NULL regions returned, normally 3 */ int pci_get_regions(struct udevice *dev, struct pci_region **iop, struct pci_region **memp, struct pci_region **prefp); @@ -1383,26 +1313,30 @@ void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); u32 dm_pci_read_bar32(const struct udevice *dev, int barnum); /** - * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address + * dm_pci_bus_to_phys() - convert a PCI bus address range to a physical address * * @dev: Device containing the PCI address * @addr: PCI address to convert + * @len: Length of the address range + * @mask: Mask to match flags for the region type * @flags: Flags for the region type (PCI_REGION_...) - * @return physical address corresponding to that PCI bus address + * Return: physical address corresponding to that PCI bus address */ -phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, - unsigned long flags); +phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, size_t len, + unsigned long mask, unsigned long flags); /** * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address * * @dev: Device containing the bus address * @addr: Physical address to convert + * @len: Length of the address range + * @mask: Mask to match flags for the region type * @flags: Flags for the region type (PCI_REGION_...) - * @return PCI bus address corresponding to that physical address + * Return: PCI bus address corresponding to that physical address */ -pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, - unsigned long flags); +pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len, + unsigned long mask, unsigned long flags); /** * dm_pci_map_bar() - get a virtual address associated with a BAR region @@ -1416,10 +1350,14 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, * * @dev: Device to check * @bar: Bar register offset (PCI_BASE_ADDRESS_...) + * @offset: Offset from the base to map + * @len: Length to map + * @mask: Mask to match flags for the region type * @flags: Flags for the region type (PCI_REGION_...) * @return: pointer to the virtual address to use or 0 on error */ -void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); +void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len, + unsigned long mask, unsigned long flags); /** * dm_pci_find_next_capability() - find a capability starting from an offset @@ -1523,28 +1461,34 @@ int dm_pci_find_ext_capability(struct udevice *dev, int cap); int dm_pci_flr(struct udevice *dev); #define dm_pci_virt_to_bus(dev, addr, flags) \ - dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) -#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ - map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ - (len), (map_flags)) + dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), 0, PCI_REGION_TYPE, (flags)) +#define dm_pci_bus_to_virt(dev, addr, len, mask, flags, map_flags) \ +({ \ + size_t _len = (len); \ + phys_addr_t phys_addr = dm_pci_bus_to_phys((dev), (addr), _len, \ + (mask), (flags)); \ + map_physmem(phys_addr, _len, (map_flags)); \ +}) #define dm_pci_phys_to_mem(dev, addr) \ - dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) + dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM) #define dm_pci_mem_to_phys(dev, addr) \ - dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) + dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM) #define dm_pci_phys_to_io(dev, addr) \ - dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) + dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO) #define dm_pci_io_to_phys(dev, addr) \ - dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) + dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO) #define dm_pci_virt_to_mem(dev, addr) \ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ - dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) + dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \ + PCI_REGION_MEM, (map_flags)) #define dm_pci_virt_to_io(dev, addr) \ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ - dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) + dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \ + PCI_REGION_IO, (map_flags)) /** * dm_pci_find_device() - find a device by vendor/device ID @@ -1553,7 +1497,7 @@ int dm_pci_flr(struct udevice *dev); * @device: Device ID * @index: 0 to find the first match, 1 for second, etc. * @devp: Returns pointer to the device, if found - * @return 0 if found, -ve on error + * Return: 0 if found, -ve on error */ int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, struct udevice **devp); @@ -1564,7 +1508,7 @@ int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, * @find_class: 3-byte (24-bit) class value to find * @index: 0 to find the first match, 1 for second, etc. * @devp: Returns pointer to the device, if found - * @return 0 if found, -ve on error + * Return: 0 if found, -ve on error */ int dm_pci_find_class(uint find_class, int index, struct udevice **devp); @@ -1676,7 +1620,7 @@ struct dm_pci_emul_ops { * @find_devfn: PCI device and function address (PCI_DEVFN()) * @containerp: Returns container device if found * @emulp: Returns emulated device if found - * @return 0 if found, -ENODEV if not found + * Return: 0 if found, -ENODEV if not found */ int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn, struct udevice **containerp, struct udevice **emulp); @@ -1686,11 +1630,17 @@ int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn, * * @emul: Emulation device to check * @devp: Returns the client device emulated by this device - * @return 0 if OK, -ENOENT if the device has no client yet + * Return: 0 if OK, -ENOENT if the device has no client yet */ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp); -#endif /* CONFIG_DM_PCI */ +/** + * board_pci_fixup_dev() - Board callback for PCI device fixups + * + * @bus: PCI bus + * @dev: PCI device + */ +extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev); /** * PCI_DEVICE - macro used to describe a specific pci device