X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fpci.h;h=797f224e2fc4d3851622bec9ac23d0b4585ff4a8;hb=92832045c54586e9dffa082ff8cd8c2ef6040757;hp=40e3c3fc6f9c6b0032b0daa00bcacee9a3567001;hpb=c4e72c4ad8b7c2db9c868bd053c25344b95900b8;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/pci.h b/include/pci.h index 40e3c3f..797f224 100644 --- a/include/pci.h +++ b/include/pci.h @@ -465,16 +465,58 @@ #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ #define PCI_EA_ES 0x00000007 /* Entry Size */ #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ +/* 9-14 map to VF BARs 0-5 respectively */ +#define PCI_EA_BEI_VF_BAR0 9 +#define PCI_EA_BEI_VF_BAR5 14 /* Base, MaxOffset registers */ /* bit 0 is reserved */ #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ +#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_RTCTL 28 /* Root Control */ +#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ +#define PCI_EXP_RTCAP 30 /* Root Capabilities */ +#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ +#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ + +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +/* Single Root I/O Virtualization Registers */ +#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ +#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ +#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ +#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ +#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ +#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ +#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ +#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ /* Include the ID list */ @@ -488,8 +530,8 @@ typedef u64 pci_addr_t; typedef u64 pci_size_t; #else -typedef u32 pci_addr_t; -typedef u32 pci_size_t; +typedef unsigned long pci_addr_t; +typedef unsigned long pci_size_t; #endif struct pci_region { @@ -531,7 +573,7 @@ typedef int pci_dev_t; * This is relevant for the following macros: * PCI_DEV, PCI_FUNC, PCI_DEVFN * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with - * the remark from above (input d in bits 15-8 instead of 7-0. + * the remark from above (input is in bits 15-8 instead of 7-0. */ #define PCI_DEV(d) (((d) >> 11) & 0x1f) #define PCI_FUNC(d) (((d) >> 8) & 0x7) @@ -540,9 +582,11 @@ typedef int pci_dev_t; #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) -#define PCI_VENDEV(v, d) (((v) << 16) | (d)) #define PCI_ANY_ID (~0) +/* Convert from Linux format to U-Boot format */ +#define PCI_TO_BDF(val) ((val) << 8) + struct pci_device_id { unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ @@ -569,8 +613,6 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS 7 - #define INDIRECT_TYPE_NO_PCIE_LINK 1 /** @@ -585,13 +627,9 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev * about a small subset of PCI devices. This is normally false. */ struct pci_controller { -#ifdef CONFIG_DM_PCI struct udevice *bus; struct udevice *ctlr; bool skip_auto_config_until_reloc; -#else - struct pci_controller *next; -#endif int first_busno; int last_busno; @@ -611,60 +649,18 @@ struct pci_controller { * for PCI controllers and a separate UCLASS (or perhaps * UCLASS_PCI_GENERIC) is used for bridges. */ - struct pci_region regions[MAX_PCI_REGIONS]; + struct pci_region *regions; int region_count; struct pci_config_table *config_table; void (*fixup_irq)(struct pci_controller *, pci_dev_t); -#ifndef CONFIG_DM_PCI - /* Low-level architecture-dependent routines */ - int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); - int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); - int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); - int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); - int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); - int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); -#endif /* Used by auto config */ struct pci_region *pci_mem, *pci_io, *pci_prefetch; - -#ifndef CONFIG_DM_PCI - int current_busno; - - void *priv_data; -#endif }; -#ifndef CONFIG_DM_PCI -static inline void pci_set_ops(struct pci_controller *hose, - int (*read_byte)(struct pci_controller*, - pci_dev_t, int where, u8 *), - int (*read_word)(struct pci_controller*, - pci_dev_t, int where, u16 *), - int (*read_dword)(struct pci_controller*, - pci_dev_t, int where, u32 *), - int (*write_byte)(struct pci_controller*, - pci_dev_t, int where, u8), - int (*write_word)(struct pci_controller*, - pci_dev_t, int where, u16), - int (*write_dword)(struct pci_controller*, - pci_dev_t, int where, u32)) { - hose->read_byte = read_byte; - hose->read_word = read_word; - hose->read_dword = read_dword; - hose->write_byte = write_byte; - hose->write_word = write_word; - hose->write_dword = write_dword; -} -#endif - -#ifdef CONFIG_PCI_INDIRECT_BRIDGE -extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); -#endif - -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) +#if defined(CONFIG_DM_PCI_COMPAT) extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, pci_addr_t addr, unsigned long flags); extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, @@ -714,15 +710,6 @@ extern int pci_hose_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 val); #endif -#ifndef CONFIG_DM_PCI -extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); -extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); -extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); -extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); -extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); -extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); -#endif - void pciauto_region_init(struct pci_region *res); void pciauto_region_align(struct pci_region *res, pci_size_t size); void pciauto_config_init(struct pci_controller *hose); @@ -741,8 +728,9 @@ void pciauto_config_init(struct pci_controller *hose); */ int pciauto_region_allocate(struct pci_region *res, pci_size_t size, pci_addr_t *bar, bool supports_64bit); +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) +#if defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, @@ -758,7 +746,6 @@ extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern struct pci_controller *pci_get_hose_head(void); -extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); @@ -789,13 +776,7 @@ int pci_find_next_ext_capability(struct pci_controller *hose, int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, int cap); -#ifdef CONFIG_PCI_FIXUP_DEV -extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, - unsigned short vendor, - unsigned short device, - unsigned short class); -#endif -#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ +#endif /* defined(CONFIG_DM_PCI_COMPAT) */ const char * pci_class_str(u8 class); int pci_last_busno(void); @@ -804,11 +785,6 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif -#ifdef CONFIG_PCIE_IMX -extern void imx_pcie_remove(void); -#endif - -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits * @@ -816,6 +792,8 @@ extern void imx_pcie_remove(void); * with devices which require hard-coded addresses, not part of the normal * PCI enumeration process. * + * This is only available if CONFIG_DM_PCI_COMPAT is enabled + * * @hose: PCI hose to use * @dev: PCI device to update * @barnum: BAR number (0-5) @@ -827,6 +805,8 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, /** * pci_read_bar32() - read the address of a bar * + * This is only available if CONFIG_DM_PCI_COMPAT is enabled + * * @hose: PCI hose to use * @dev: PCI device to inspect * @barnum: BAR number (0-5) @@ -837,6 +817,8 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); /** * pci_hose_find_devices() - Find devices by vendor/device ID * + * This is only available if CONFIG_DM_PCI_COMPAT is enabled + * * @hose: PCI hose to search * @busnum: Bus number to search * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record @@ -847,7 +829,6 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); */ pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, struct pci_device_id *ids, int *indexp); -#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ /* Access sizes for PCI reads and writes */ enum pci_size_t { @@ -858,25 +839,32 @@ enum pci_size_t { struct udevice; -#ifdef CONFIG_DM_PCI /** - * struct pci_child_platdata - information stored about each PCI device + * struct pci_child_plat - information stored about each PCI device * * Every device on a PCI bus has this per-child data. * - * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a + * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a * PCI bus (i.e. UCLASS_PCI) * * @devfn: Encoded device and function index - see PCI_DEVFN() * @vendor: PCI vendor ID (see pci_ids.h) * @device: PCI device ID (see pci_ids.h) * @class: PCI class, 3 bytes: (base, sub, prog-if) + * @is_virtfn: True for Virtual Function device + * @pfdev: Handle to Physical Function device + * @virtid: Virtual Function Index */ -struct pci_child_platdata { +struct pci_child_plat { int devfn; unsigned short vendor; unsigned short device; unsigned int class; + + /* Variables for CONFIG_PCI_SRIOV */ + bool is_virtfn; + struct udevice *pfdev; + int virtid; }; /* PCI bus operations */ @@ -887,7 +875,7 @@ struct dm_pci_ops { * PCI buses must support reading and writing configuration values * so that the bus can be scanned and its devices configured. * - * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. + * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always. * If bridges exist it is possible to use the top-level bus to * access a sub-bus. In that case @bus will be the top-level bus * and PCI_BUS(bdf) will be a different (higher) value @@ -924,7 +912,7 @@ struct dm_pci_ops { * @dev: Device to check * @return bus/device/function value (see PCI_BDF()) */ -pci_dev_t dm_pci_get_bdf(struct udevice *dev); +pci_dev_t dm_pci_get_bdf(const struct udevice *dev); /** * pci_bind_bus_devices() - scan a PCI bus and bind devices @@ -1023,7 +1011,7 @@ int pci_get_ff(enum pci_size_t size); * @devp: Returns matching device if found * @return 0 if found, -ENODEV if not */ -int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, +int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids, int *indexp, struct udevice **devp); /** @@ -1035,7 +1023,7 @@ int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, * @devp: Returns matching device if found * @return 0 if found, -ENODEV if not */ -int pci_find_device_id(struct pci_device_id *ids, int index, +int pci_find_device_id(const struct pci_device_id *ids, int index, struct udevice **devp); /** @@ -1067,7 +1055,7 @@ int dm_pci_hose_probe_bus(struct udevice *bus); * @size: Access size * @return 0 if OK, -ve on error */ -int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, +int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, unsigned long *valuep, enum pci_size_t size); /** @@ -1102,12 +1090,12 @@ int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, * Driver model PCI config access functions. Use these in preference to others * when you have a valid device */ -int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, - enum pci_size_t size); +int dm_pci_read_config(const struct udevice *dev, int offset, + unsigned long *valuep, enum pci_size_t size); -int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); -int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); -int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); +int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep); +int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep); +int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep); int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, enum pci_size_t size); @@ -1189,6 +1177,25 @@ int pci_generic_mmap_read_config( ulong *valuep, enum pci_size_t size); +#if defined(CONFIG_PCI_SRIOV) +/** + * pci_sriov_init() - Scan Virtual Function devices + * + * @pdev: Physical Function udevice handle + * @vf_en: Number of Virtual Function devices to enable + * @return 0 on success, -ve on error + */ +int pci_sriov_init(struct udevice *pdev, int vf_en); + +/** + * pci_sriov_get_totalvfs() - Get total available Virtual Function devices + * + * @pdev: Physical Function udevice handle + * @return count on success, -ve on error + */ +int pci_sriov_get_totalvfs(struct udevice *pdev); +#endif + #ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, @@ -1294,7 +1301,8 @@ struct udevice *pci_get_controller(struct udevice *dev); */ int pci_get_regions(struct udevice *dev, struct pci_region **iop, struct pci_region **memp, struct pci_region **prefp); - +int +pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index); /** * dm_pci_write_bar32() - Write the address of a BAR * @@ -1313,7 +1321,7 @@ void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); * @barnum: Bar number to read (numbered from 0) * @return: value of BAR */ -u32 dm_pci_read_bar32(struct udevice *dev, int barnum); +u32 dm_pci_read_bar32(const struct udevice *dev, int barnum); /** * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address @@ -1623,7 +1631,13 @@ int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn, */ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp); -#endif /* CONFIG_DM_PCI */ +/** + * board_pci_fixup_dev() - Board callback for PCI device fixups + * + * @bus: PCI bus + * @dev: PCI device + */ +extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev); /** * PCI_DEVICE - macro used to describe a specific pci device