X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fmmc.h;h=82562193cc489cdfecab3136ef42f9123d041af3;hb=2493ce6258a59881b702cbe255db9e53f1e3fd13;hp=a8901bffc7b6f852d0942018d7f9e1997d370c46;hpb=01298da31d92ecc46cf9130d8cff68bc51698197;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/mmc.h b/include/mmc.h index a8901bf..8256219 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -1,20 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2008,2010 Freescale Semiconductor, Inc * Andy Fleming * * Based (loosely) on the Linux code - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _MMC_H_ #define _MMC_H_ +#include #include #include #include +#include #include +struct bd_info; + +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#define MMC_SUPPORTS_TUNING +#endif +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) +#define MMC_SUPPORTS_TUNING +#endif + /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ #define SD_VERSION_SD (1U << 31) #define MMC_VERSION_MMC (1U << 30) @@ -47,6 +57,7 @@ #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) +#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0) #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) @@ -57,6 +68,12 @@ #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) +#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400) +#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES) + +#define MMC_CAP_NONREMOVABLE BIT(14) +#define MMC_CAP_NEEDS_POLL BIT(15) +#define MMC_CAP_CD_ACTIVE_HIGH BIT(16) #define MMC_MODE_8BIT BIT(30) #define MMC_MODE_4BIT BIT(29) @@ -207,17 +224,23 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_WR_REL_PARAM 166 /* R */ #define EXT_CSD_WR_REL_SET 167 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */ +#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */ +#define EXT_CSD_BOOT_WP_STATUS 174 /* R */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 #define EXT_CSD_PART_CONF 179 /* R/W */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_REV 192 /* RO */ #define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ #define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ /* @@ -241,6 +264,10 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) /* SDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ @@ -248,10 +275,13 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ +#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */ #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ #define EXT_CSD_TIMING_HS 1 /* HS */ #define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ +#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) @@ -306,13 +336,21 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define ENHNCD_SUPPORT (0x2) #define PART_ENH_ATTRIB (0x1f) +#define MMC_QUIRK_RETRY_SEND_CID BIT(0) +#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) +#define MMC_QUIRK_RETRY_APP_CMD BIT(2) + enum mmc_voltage { MMC_SIGNAL_VOLTAGE_000 = 0, - MMC_SIGNAL_VOLTAGE_120, - MMC_SIGNAL_VOLTAGE_180, - MMC_SIGNAL_VOLTAGE_330 + MMC_SIGNAL_VOLTAGE_120 = 1, + MMC_SIGNAL_VOLTAGE_180 = 2, + MMC_SIGNAL_VOLTAGE_330 = 4, }; +#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\ + MMC_SIGNAL_VOLTAGE_180 |\ + MMC_SIGNAL_VOLTAGE_330) + /* Maximum block size for MMC */ #define MMC_MAX_BLOCK_LEN 512 @@ -340,7 +378,7 @@ struct mmc_uclass_priv { * @dev: Device * @return associated mmc struct pointer if available, else NULL */ -struct mmc *mmc_get_mmc_dev(struct udevice *dev); +struct mmc *mmc_get_mmc_dev(const struct udevice *dev); /* End of driver model support */ @@ -376,6 +414,14 @@ struct mmc; #if CONFIG_IS_ENABLED(DM_MMC) struct dm_mmc_ops { /** + * deferred_probe() - Some configurations that need to be deferred + * to just before enumerating the device + * + * @dev: Device to init + * @return 0 if Ok, -ve if error + */ + int (*deferred_probe)(struct udevice *dev); + /** * send_cmd() - Send a command to the MMC device * * @dev: Device to receive the command @@ -395,14 +441,6 @@ struct dm_mmc_ops { int (*set_ios)(struct udevice *dev); /** - * send_init_stream() - send the initialization stream: 74 clock cycles - * This is used after power up before sending the first command - * - * @dev: Device to update - */ - void (*send_init_stream)(struct udevice *dev); - - /** * get_cd() - See whether a card is present * * @dev: Device to check @@ -418,6 +456,7 @@ struct dm_mmc_ops { */ int (*get_wp)(struct udevice *dev); +#ifdef MMC_SUPPORTS_TUNING /** * execute_tuning() - Start the tuning process * @@ -426,6 +465,7 @@ struct dm_mmc_ops { * @return 0 if OK, -ve on error */ int (*execute_tuning)(struct udevice *dev, uint opcode); +#endif /** * wait_dat0() - wait until dat0 is in the target state @@ -433,10 +473,38 @@ struct dm_mmc_ops { * * @dev: Device to check * @state: target state - * @timeout: timeout in us + * @timeout_us: timeout in us * @return 0 if dat0 is in the target state, -ve on error */ - int (*wait_dat0)(struct udevice *dev, int state, int timeout); + int (*wait_dat0)(struct udevice *dev, int state, int timeout_us); + +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + /* set_enhanced_strobe() - set HS400 enhanced strobe */ + int (*set_enhanced_strobe)(struct udevice *dev); +#endif + + /** + * host_power_cycle - host specific tasks in power cycle sequence + * Called between mmc_power_off() and + * mmc_power_on() + * + * @dev: Device to check + * @return 0 if not present, 1 if present, -ve on error + */ + int (*host_power_cycle)(struct udevice *dev); + + /** + * get_b_max - get maximum length of single transfer + * Called before reading blocks from the card, + * useful for system which have e.g. DMA limits + * on various memory ranges. + * + * @dev: Device to check + * @dst: Destination buffer in memory + * @blkcnt: Total number of blocks in this transfer + * @return maximum number of blocks for this transfer + */ + int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt); }; #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) @@ -444,19 +512,24 @@ struct dm_mmc_ops { int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data); int dm_mmc_set_ios(struct udevice *dev); -void dm_mmc_send_init_stream(struct udevice *dev); int dm_mmc_get_cd(struct udevice *dev); int dm_mmc_get_wp(struct udevice *dev); int dm_mmc_execute_tuning(struct udevice *dev, uint opcode); -int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout); +int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us); +int dm_mmc_host_power_cycle(struct udevice *dev); +int dm_mmc_deferred_probe(struct udevice *dev); +int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt); /* Transition functions for compatibility */ int mmc_set_ios(struct mmc *mmc); -void mmc_send_init_stream(struct mmc *mmc); int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); int mmc_execute_tuning(struct mmc *mmc, uint opcode); -int mmc_wait_dat0(struct mmc *mmc, int state, int timeout); +int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us); +int mmc_set_enhanced_strobe(struct mmc *mmc); +int mmc_host_power_cycle(struct mmc *mmc); +int mmc_deferred_probe(struct mmc *mmc); +int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt); #else struct mmc_ops { @@ -466,6 +539,8 @@ struct mmc_ops { int (*init)(struct mmc *mmc); int (*getcd)(struct mmc *mmc); int (*getwp)(struct mmc *mmc); + int (*host_power_cycle)(struct mmc *mmc); + int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt); }; #endif @@ -490,17 +565,18 @@ struct sd_ssr { enum bus_mode { MMC_LEGACY, - SD_LEGACY, MMC_HS, SD_HS, + MMC_HS_52, + MMC_DDR_52, UHS_SDR12, UHS_SDR25, UHS_SDR50, - UHS_SDR104, UHS_DDR50, - MMC_HS_52, - MMC_DDR_52, + UHS_SDR104, MMC_HS_200, + MMC_HS_400, + MMC_HS_400_ES, MMC_MODES_END }; @@ -509,8 +585,20 @@ void mmc_dump_capabilities(const char *text, uint caps); static inline bool mmc_is_mode_ddr(enum bus_mode mode) { - if ((mode == MMC_DDR_52) || (mode == UHS_DDR50)) + if (mode == MMC_DDR_52) + return true; +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) + else if (mode == UHS_DDR50) return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + else if (mode == MMC_HS_400) + return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + else if (mode == MMC_HS_400_ES) + return true; +#endif else return false; } @@ -521,7 +609,11 @@ static inline bool mmc_is_mode_ddr(enum bus_mode mode) static inline bool supports_uhs(uint caps) { +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) return (caps & UHS_CAPS) ? true : false; +#else + return false; +#endif } /* @@ -542,6 +634,7 @@ struct mmc { bool clk_disable; /* true if the clock can be turned off */ uint bus_width; uint clock; + uint saved_clock; enum mmc_voltage signal_voltage; uint card_caps; uint host_caps; @@ -556,20 +649,30 @@ struct mmc { u8 part_attr; u8 wr_rel_set; u8 part_config; + u8 gen_cmd6_time; /* units: 10 ms */ + u8 part_switch_time; /* units: 10 ms */ uint tran_speed; uint legacy_speed; /* speed for the legacy mode provided by the card */ uint read_bl_len; +#if CONFIG_IS_ENABLED(MMC_WRITE) uint write_bl_len; uint erase_grp_size; /* in 512-byte sectors */ +#endif +#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) uint hc_wp_grp_size; /* in 512-byte sectors */ +#endif +#if CONFIG_IS_ENABLED(MMC_WRITE) struct sd_ssr ssr; /* SD status register */ +#endif u64 capacity; u64 capacity_user; u64 capacity_boot; u64 capacity_rpmb; u64 capacity_gp[4]; +#ifndef CONFIG_SPL_BUILD u64 enh_user_start; u64 enh_user_size; +#endif #if !CONFIG_IS_ENABLED(BLK) struct blk_desc block_dev; #endif @@ -585,12 +688,15 @@ struct mmc { #endif #endif u8 *ext_csd; + u32 cardtype; /* cardtype read from the MMC */ + enum mmc_voltage current_voltage; enum bus_mode selected_mode; /* mode currently used */ enum bus_mode best_mode; /* best mode is the supported mode with the * highest bandwidth. It may not always be the * operating mode due to limitations when * accessing the boot partitions */ + u32 quirks; }; struct mmc_hwpart_conf { @@ -638,11 +744,37 @@ void mmc_destroy(struct mmc *mmc); * @return 0 if OK, -ve on error */ int mmc_unbind(struct udevice *dev); -int mmc_initialize(bd_t *bis); +int mmc_initialize(struct bd_info *bis); +int mmc_init_device(int num); int mmc_init(struct mmc *mmc); +int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error); + +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +int mmc_deinit(struct mmc *mmc); +#endif + +/** + * mmc_of_parse() - Parse the device tree to get the capabilities of the host + * + * @dev: MMC device + * @cfg: MMC configuration + * @return 0 if OK, -ve on error + */ +int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg); + int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); /** + * mmc_voltage_to_mv() - Convert a mmc_voltage in mV + * + * @voltage: The mmc_voltage to convert + * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value) + */ +int mmc_voltage_to_mv(enum mmc_voltage voltage); + +/** * mmc_set_clock() - change the bus clock * @mmc: MMC struct * @clock: bus frequency in Hz @@ -651,6 +783,9 @@ int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); */ int mmc_set_clock(struct mmc *mmc, uint clock, bool disable); +#define MMC_CLK_ENABLE false +#define MMC_CLK_DISABLE true + struct mmc *find_mmc_device(int dev_num); int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); @@ -689,18 +824,47 @@ int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, unsigned short cnt, unsigned char *key); int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, unsigned short cnt, unsigned char *key); + +/** + * mmc_rpmb_route_frames() - route RPMB data frames + * @mmc Pointer to a MMC device struct + * @req Request data frames + * @reqlen Length of data frames in bytes + * @rsp Supplied buffer for response data frames + * @rsplen Length of supplied buffer for response data frames + * + * The RPMB data frames are routed to/from some external entity, for + * example a Trusted Exectuion Environment in an arm TrustZone protected + * secure world. It's expected that it's the external entity who is in + * control of the RPMB key. + * + * Returns 0 on success, < 0 on error. + */ +int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen, + void *rsp, unsigned long rsplen); + #ifdef CONFIG_CMD_BKOPS_ENABLE int mmc_set_bkops_enable(struct mmc *mmc); #endif /** * Start device initialization and return immediately; it does not block on + * polling OCR (operation condition register) status. Useful for checking + * the presence of SD/eMMC when no card detect logic is available. + * + * @param mmc Pointer to a MMC device struct + * @return 0 on success, <0 on error. + */ +int mmc_get_op_cond(struct mmc *mmc); + +/** + * Start device initialization and return immediately; it does not block on * polling OCR (operation condition register) status. Then you should call * mmc_init, which would block on polling OCR status and complete the device * initializatin. * * @param mmc Pointer to a MMC device struct - * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. + * @return 0 on success, <0 on error. */ int mmc_start_init(struct mmc *mmc); @@ -723,14 +887,19 @@ void mmc_set_preinit(struct mmc *mmc, int preinit); #else #define mmc_host_is_spi(mmc) 0 #endif -struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); void board_mmc_power_init(void); -int board_mmc_init(bd_t *bis); -int cpu_mmc_init(bd_t *bis); +int board_mmc_init(struct bd_info *bis); +int cpu_mmc_init(struct bd_info *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +# ifdef CONFIG_SYS_MMC_ENV_PART +extern uint mmc_get_env_part(struct mmc *mmc); +# endif int mmc_get_env_dev(void); +/* Minimum partition switch timeout in units of 10-milliseconds */ +#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */ + /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 @@ -744,4 +913,29 @@ int mmc_get_env_dev(void); */ struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); +/** + * mmc_send_ext_csd() - read the extended CSD register + * + * @mmc: MMC device + * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by + * the caller, e.g. using + * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN) + * Return: 0 for success + */ +int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd); + +/** + * mmc_boot_wp() - power on write protect boot partitions + * + * The boot partitions are write protected until the next power cycle. + * + * Return: 0 for success + */ +int mmc_boot_wp(struct mmc *mmc); + +static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data) +{ + return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; +} + #endif /* _MMC_H_ */