X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Ffsl_sec.h;h=c0d2c7e8667921727be914d2cb42f29eba37240e;hb=6864fc8704661878294d1f0f981f47e864ef470f;hp=b6e6f04a34ce52d0da088b84f19ac5bdf2ae0ebf;hpb=1606b34aa50804227806971dbb6b82ea0bf81f55;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index b6e6f04..c0d2c7e 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -1,8 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Common internal memory map for some Freescale SoCs
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
  */
 
 #ifndef __FSL_SEC_H
@@ -23,7 +23,7 @@
 #define sec_in16(a)       in_be16(a)
 #define sec_clrbits32     clrbits_be32
 #define sec_setbits32     setbits_be32
-#else
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
 
@@ -32,10 +32,20 @@
 /* RNG4 TRNG test registers */
 struct rng4tst {
 #define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
+						    both entropy shifter and
+						    statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
+						    entropy shifter and
+						    statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
+						    entropy shifter, raw data
+						    in statistical checker */
+#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
 	u32 rtmctl;		/* misc. control register */
 	u32 rtscmisc;		/* statistical check misc. register */
 	u32 rtpkrrng;		/* poker range register */
-#define RTSDCTL_ENT_DLY_MIN	1200
+#define RTSDCTL_ENT_DLY_MIN	3200
 #define RTSDCTL_ENT_DLY_MAX	12800
 	union {
 		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
@@ -49,12 +59,16 @@ struct rng4tst {
 		u32 rttotsam;	/* PRGM=0: total samples register */
 	};
 	u32 rtfreqmin;		/* frequency count min. limit register */
+#define RTFRQMAX_DISABLE       (1 << 20)
 	union {
 		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
 		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
 	};
 	u32 rsvd1[40];
 #define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
+#define RNG_STATE1_HANDLE_INSTANTIATED	0x00000002
+#define RNG_STATE_HANDLE_MASK	\
+	(RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
 	u32 rdsta;		/*RNG DRNG Status Register*/
 	u32 rsvd2[15];
 };
@@ -79,25 +93,25 @@ typedef struct ccsr_sec {
 	struct {
 		u32	ms;	/* DECO LIODN Register, MS */
 		u32	ls;	/* DECO LIODN Register, LS */
-	} decoliodnr[8];
-	u8	res4[0x40];
+	} decoliodnr[16];
 	u32	dar;		/* DECO Avail Register */
 	u32	drr;		/* DECO Reset Register */
 	u8	res5[0x4d8];
 	struct rng4tst rng;	/* RNG Registers */
-	u8	res11[0x8a0];
+	u8	res6[0x8a0];
 	u32	crnr_ms;	/* CHA Revision Number Register, MS */
 	u32	crnr_ls;	/* CHA Revision Number Register, LS */
 	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
 	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
-	u8	res6[0x10];
+	u8	res7[0x10];
 	u32	far_ms;		/* Fault Address Register, MS */
 	u32	far_ls;		/* Fault Address Register, LS */
 	u32	falr;		/* Fault Address LIODN Register */
 	u32	fadr;		/* Fault Address Detail Register */
-	u8	res7[0x4];
+	u8	res8[0x4];
 	u32	csta;		/* CAAM Status Register */
-	u8	res8[0x8];
+	u32	smpart;		/* Secure Memory Partition Parameters */
+	u32	smvid;		/* Secure Memory Version ID */
 	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
 	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
 	u32	chavid_ms;	/* CHA Version ID Register, MS */
@@ -106,10 +120,18 @@ typedef struct ccsr_sec {
 	u32	chanum_ls;	/* CHA Number Register, LS */
 	u32	secvid_ms;	/* SEC Version ID Register, MS */
 	u32	secvid_ls;	/* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	u8	res9[0x6f020];
+#else
 	u8	res9[0x6020];
+#endif
 	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
 	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	u8	res10[0x8ffd8];
+#else
 	u8	res10[0x8fd8];
+#endif
 } ccsr_sec_t;
 
 #define SEC_CTPR_MS_AXI_LIODN		0x08000000
@@ -135,7 +157,8 @@ typedef struct ccsr_sec {
 #define CONFIG_JRSTARTR_JR0		0x00000001
 
 struct jr_regs {
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && \
+	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
 	u32 irba_l;
 	u32 irba_h;
 #else
@@ -148,7 +171,8 @@ struct jr_regs {
 	u32 irsa;
 	u32 rsvd3;
 	u32 irja;
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && \
+	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
 	u32 orba_l;
 	u32 orba_h;
 #else
@@ -180,13 +204,12 @@ struct jr_regs {
  * related information
  */
 struct sg_entry {
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && \
+	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
 	uint32_t addr_lo;	/* Memory Address - lo */
-	uint16_t addr_hi;	/* Memory Address of start of buffer - hi */
-	uint16_t reserved_zero;
+	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
 #else
-	uint16_t reserved_zero;
-	uint16_t addr_hi;	/* Memory Address of start of buffer - hi */
+	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
 	uint32_t addr_lo;	/* Memory Address - lo */
 #endif
 
@@ -201,6 +224,97 @@ struct sg_entry {
 #define SG_ENTRY_OFFSET_SHIFT	0
 };
 
+#define BLOB_SIZE(x)		((x) + 32 + 16) /* Blob buffer size */
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
+/* Job Ring Base Address */
+#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
+/* Secure Memory Offset varies accross versions */
+#define SM_V1_OFFSET 0x0f4
+#define SM_V2_OFFSET 0xa00
+/*Secure Memory Versioning */
+#define SMVID_V2 0x20105
+#define SM_VERSION(x)  (x < SMVID_V2 ? 1 : 2)
+#define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
+/* CAAM Job Ring 0 Registers */
+/* Secure Memory Partition Owner register */
+#define SMCSJR_PO		(3 << 6)
+/* JR Allocation Error */
+#define SMCSJR_AERR		(3 << 12)
+/* Secure memory partition 0 page 0 owner register */
+#define CAAM_SMPO_0	    (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
+/* Secure memory command register */
+#define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
+/* Secure memory command status register */
+#define CAAM_SMCSJR(v, jr)  (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
+/* Secure memory access permissions register */
+#define CAAM_SMAPJR(v, jr, y) \
+	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
+/* Secure memory access group 2 register */
+#define CAAM_SMAG2JR(v, jr, y) \
+	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
+/* Secure memory access group 1 register */
+#define CAAM_SMAG1JR(v, jr, y)  \
+	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
+
+/* Commands and macros for secure memory */
+#define SM_CMD(v)		(v == 1 ? 0x0 : 0x1E4)
+#define SM_STATUS(v)		(v == 1 ? 0x8 : 0x1EC)
+#define SM_PERM(v)		(v == 1 ?  0x10 : 0x4)
+#define SM_GROUP2(v)		(v == 1 ? 0x14 : 0x8)
+#define SM_GROUP1(v)		(v == 1 ? 0x18 : 0xC)
+#define CMD_PAGE_ALLOC		0x1
+#define CMD_PAGE_DEALLOC	0x2
+#define CMD_PART_DEALLOC	0x3
+#define CMD_INQUIRY		0x5
+#define CMD_COMPLETE		(3 << 14)
+#define PAGE_AVAILABLE		0
+#define PAGE_OWNED		(3 << 6)
+#define PAGE(x)			(x << 16)
+#define PARTITION(x)		(x << 8)
+#define PARTITION_OWNER(x)	(0x3 << (x*2))
+
+/* Address of secure 4kbyte pages */
+#define SEC_MEM_PAGE0		CAAM_ARB_BASE_ADDR
+#define SEC_MEM_PAGE1		(CAAM_ARB_BASE_ADDR + 0x1000)
+#define SEC_MEM_PAGE2		(CAAM_ARB_BASE_ADDR + 0x2000)
+#define SEC_MEM_PAGE3		(CAAM_ARB_BASE_ADDR + 0x3000)
+
+#define JR_MID			2               /* Matches ROM configuration */
+#define KS_G1			(1 << JR_MID)   /* CAAM only */
+#define PERM			0x0000B008      /* Clear on release, lock SMAP
+						 * lock SMAG group 1 Blob */
+
+/* HAB WRAPPED KEY header */
+#define WRP_HDR_SIZE		0x08
+#define HDR_TAG			0x81
+#define HDR_PAR			0x41
+/* HAB WRAPPED KEY Data */
+#define HAB_MOD			0x66
+#define HAB_ALG			0x55
+#define HAB_FLG			0x00
+
+/* Partition and Page IDs */
+#define PARTITION_1	1
+#define PAGE_1			1
+
+#define ERROR_IN_PAGE_ALLOC	1
+#define ECONSTRJDESC   -1
+
+#endif
+
+/* blob_dek:
+ * Encapsulates the src in a secure blob and stores it dst
+ * @src: reference to the plaintext
+ * @dst: reference to the output adrress
+ * @len: size in bytes of src
+ * @return: 0 on success, error otherwise
+ */
+int blob_dek(const u8 *src, u8 *dst, u8 len);
+
+#if defined(CONFIG_ARCH_C29X)
+int sec_init_idx(uint8_t);
+#endif
 int sec_init(void);
 #endif