X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Ffsl_ddr_sdram.h;h=a7272e4be7059eae41308620b4e181870255e898;hb=a29491ade0adf3dbb9dc51be8b45530edde1f1df;hp=1404c5793607089c519c8d8f6dfe0fc9ef18fe57;hpb=bf50ac918bfbc0042e43b0a5c87cfa9dd4351e0a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 1404c57..a7272e4 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -1,7 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright 2008-2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0 + * Copyright 2008-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP Semiconductor */ #ifndef FSL_DDR_MEMCTL_H @@ -173,6 +173,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_V0PT9_EN 0x40000000 #define DDR_CDR1_ODT_SHIFT 17 #define DDR_CDR1_ODT_MASK 0x6 #define DDR_CDR2_ODT_MASK 0x1 @@ -365,6 +366,7 @@ typedef struct memctl_options_s { unsigned int quad_rank_present; unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ unsigned int x4_en; /* enable x4 devices */ + unsigned int package_3ds; /* Global Timing Parameters */ unsigned int cas_latency_override; @@ -407,6 +409,7 @@ typedef struct memctl_options_s { unsigned int rcw_override; unsigned int rcw_1; unsigned int rcw_2; + unsigned int rcw_3; /* control register 1 */ unsigned int ddr_cdr1; unsigned int ddr_cdr2; @@ -476,4 +479,12 @@ typedef struct fixed_ddr_parm{ int max_freq; fsl_ddr_cfg_regs_t *ddr_settings; } fixed_ddr_parm_t; + +/** + * fsl_initdram() - Set up the SDRAM + * + * Return: 0 if OK, -ve on error + */ +int fsl_initdram(void); + #endif