X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Ffdtdec.h;h=c26df50543a82b2266fa68cb82b6eb382e4a8530;hb=19ca29f3ff5811e058360aa275208d219b3078c2;hp=422a155e9733bf5e5e3a14d73c864ba300c79bbc;hpb=6cd2602d61fc4bc172fd99dcbe9b930428992331;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/fdtdec.h b/include/fdtdec.h index 422a155..c26df50 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1,6 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (c) 2011 The Chromium OS Authors. - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __fdtdec_h @@ -14,7 +14,7 @@ * changes to support FDT are minimized. */ -#include +#include #include /* @@ -24,13 +24,15 @@ typedef phys_addr_t fdt_addr_t; typedef phys_size_t fdt_size_t; #ifdef CONFIG_PHYS_64BIT -#define FDT_ADDR_T_NONE (-1ULL) +#define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) #define fdt_size_to_cpu(reg) be64_to_cpu(reg) +typedef fdt64_t fdt_val_t; #else #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) #define fdt_size_to_cpu(reg) be32_to_cpu(reg) +typedef fdt32_t fdt_val_t; #endif /* Information obtained about memory from the FDT */ @@ -39,12 +41,18 @@ struct fdt_memory { fdt_addr_t end; }; +struct bd_info; + #ifdef CONFIG_SPL_BUILD #define SPL_BUILD 1 #else #define SPL_BUILD 0 #endif +#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) +extern phys_addr_t prior_stage_fdt_address; +#endif + /* * Information about a resource. start is the first address of the resource * and end is the last address (inclusive). The length of the resource will @@ -119,12 +127,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ - COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ - COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */ - COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */ - COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ - COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ - COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, /* Tegra124 XUSB pad controller */ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, @@ -134,16 +136,12 @@ enum fdt_compat_id { COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ - COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ - COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ - COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ @@ -151,13 +149,24 @@ enum fdt_compat_id { COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ - COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ + COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* SoCFPGA hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, /* SoCFPGA lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* SoCFPGA fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ + COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */ + COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */ + COMPAT_ALTERA_SOCFPGA_CLK_INIT, /* SOCFPGA Arria 10 clk init */ COMPAT_COUNT, }; @@ -299,11 +308,13 @@ int fdtdec_next_compatible_subnode(const void *blob, int node, * @param na the number of cells used to represent an address * @param ns the number of cells used to represent a size * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, const char *prop_name, int index, int na, int ns, - fdt_size_t *sizep); + fdt_size_t *sizep, bool translate); /* * Look up an address property in a node and return the parsed address, and @@ -319,10 +330,13 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, * @param prop_name name of property to find * @param index which address to retrieve from a list of addresses. Often 0. * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, - int node, const char *prop_name, int index, fdt_size_t *sizep); + int node, const char *prop_name, int index, fdt_size_t *sizep, + bool translate); /* * Look up an address property in a node and return the parsed address, and @@ -342,10 +356,13 @@ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, * @param prop_name name of property to find * @param index which address to retrieve from a list of addresses. Often 0. * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, - const char *prop_name, int index, fdt_size_t *sizep); + const char *prop_name, int index, fdt_size_t *sizep, + bool translate); /* * Look up an address property in a node and return the parsed address. @@ -786,57 +803,6 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node, const char *prop_name, int count); /** - * Look up a property in a node which contains a memory region address and - * size. Then return a pointer to this address. - * - * The property must hold one address with a length. This is only tested on - * 32-bit machines. - * - * @param blob FDT blob - * @param node node to examine - * @param prop_name name of property to find - * @param basep Returns base address of region - * @param size Returns size of region - * @return 0 if ok, -1 on error (property not found) - */ -int fdtdec_decode_region(const void *blob, int node, const char *prop_name, - fdt_addr_t *basep, fdt_size_t *sizep); - -enum fmap_compress_t { - FMAP_COMPRESS_NONE, - FMAP_COMPRESS_LZO, -}; - -enum fmap_hash_t { - FMAP_HASH_NONE, - FMAP_HASH_SHA1, - FMAP_HASH_SHA256, -}; - -/* A flash map entry, containing an offset and length */ -struct fmap_entry { - uint32_t offset; - uint32_t length; - uint32_t used; /* Number of bytes used in region */ - enum fmap_compress_t compress_algo; /* Compression type */ - enum fmap_hash_t hash_algo; /* Hash algorithm */ - const uint8_t *hash; /* Hash value */ - int hash_size; /* Hash size */ -}; - -/** - * Read a flash entry from the fdt - * - * @param blob FDT blob - * @param node Offset of node to read - * @param name Name of node being read - * @param entry Place to put offset and size of this node - * @return 0 if ok, -ve on error - */ -int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, - struct fmap_entry *entry); - -/** * Obtain an indexed resource from a device property. * * @param fdt FDT blob @@ -866,34 +832,6 @@ int fdt_get_named_resource(const void *fdt, int node, const char *property, const char *prop_names, const char *name, struct fdt_resource *res); -/** - * Decode a named region within a memory bank of a given type. - * - * This function handles selection of a memory region. The region is - * specified as an offset/size within a particular type of memory. - * - * The properties used are: - * - * -memory for the name of the memory bank - * -offset for the offset in that bank - * - * The property value must have an offset and a size. The function checks - * that the region is entirely within the memory bank.5 - * - * @param blob FDT blob - * @param node Node containing the properties (-1 for /config) - * @param mem_type Type of memory to use, which is a name, such as - * "u-boot" or "kernel". - * @param suffix String to append to the memory/offset - * property names - * @param basep Returns base of region - * @param sizep Returns size of region - * @return 0 if OK, -ive on error - */ -int fdtdec_decode_memory_region(const void *blob, int node, - const char *mem_type, const char *suffix, - fdt_addr_t *basep, fdt_size_t *sizep); - /* Display timings from linux include/video/display_timing.h */ enum display_flags { DISPLAY_FLAGS_HSYNC_LOW = 1 << 0, @@ -954,6 +892,7 @@ struct display_timing { struct timing_entry vsync_len; /* ver. sync len */ enum display_flags flags; /* display flags */ + bool hdmi_monitor; /* is hdmi monitor? */ }; /** @@ -971,9 +910,86 @@ struct display_timing { */ int fdtdec_decode_display_timing(const void *blob, int node, int index, struct display_timing *config); + +/** + * fdtdec_setup_mem_size_base() - decode and setup gd->ram_size and + * gd->ram_start + * + * Decode the /memory 'reg' property to determine the size and start of the + * first memory bank, populate the global data with the size and start of the + * first bank of memory. + * + * This function should be called from a boards dram_init(). This helper + * function allows for boards to query the device tree for DRAM size and start + * address instead of hard coding the value in the case where the memory size + * and start address cannot be detected automatically. + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_mem_size_base(void); + +/** + * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram + * + * Decode the /memory 'reg' property to determine the address and size of the + * memory banks. Use this data to populate the global data board info with the + * phys address and size of memory banks. + * + * This function should be called from a boards dram_init_banksize(). This + * helper function allows for boards to query the device tree for memory bank + * information instead of hard coding the information in cases where it cannot + * be detected automatically. + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_memory_banksize(void); + /** * Set up the device tree ready for use */ int fdtdec_setup(void); +/** + * Board-specific FDT initialization. Returns the address to a device tree blob. + * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined + * and the board implements it. + */ + +/* + * Decode the size of memory + * + * RAM size is normally set in a /memory node and consists of a list of + * (base, size) cells in the 'reg' property. This information is used to + * determine the total available memory as well as the address and size + * of each bank. + * + * Optionally the memory configuration can vary depending on a board id, + * typically read from strapping resistors or an EEPROM on the board. + * + * Finally, memory size can be detected (within certain limits) by probing + * the available memory. It is safe to do so within the limits provides by + * the board's device tree information. This makes it possible to produce + * boards with different memory sizes, where the device tree specifies the + * maximum memory configuration, and the smaller memory configuration is + * probed. + * + * This function decodes that information, returning the memory base address, + * size and bank information. See the memory.txt binding for full + * documentation. + * + * @param blob Device tree blob + * @param area Name of node to check (NULL means "/memory") + * @param board_id Board ID to look up + * @param basep Returns base address of first memory bank (NULL to + * ignore) + * @param sizep Returns total memory size (NULL to ignore) + * @param bd Updated with the memory bank information (NULL to skip) + * @return 0 if OK, -ve on error + */ +int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, + phys_addr_t *basep, phys_size_t *sizep, + struct bd_info *bd); + #endif