X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fzylonite.h;h=1e03b0180d96c4417d5e0693ff525ae0830277f6;hb=0ce8437f3006f86d093f83120c64f657bbac3c31;hp=6febeeafabb53e2714047ba5b6b1a5175baed2f2;hpb=b03d92e5584935886ff91d5aa0755dc8888b7187;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 6febeea..1e03b01 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -35,6 +35,7 @@
  * (easy to change)
  */
 #define CONFIG_CPU_MONAHANS	1	/* Intel Monahan CPU    */
+#define	CONFIG_CPU_PXA320
 #define CONFIG_ZYLONITE		1	/* Zylonite board       */
 
 /* #define CONFIG_LCD		1 */
@@ -44,14 +45,15 @@
 #undef CONFIG_MMC
 #define BOARD_LATE_INIT		1
 
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -59,7 +61,7 @@
 
 #undef TURN_ON_ETHERNET
 #ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111 1
 # define CONFIG_SMC91111_BASE   0x14000300
 # define CONFIG_SMC91111_EXT_PHY
 # define CONFIG_SMC_USE_32_BIT
@@ -69,6 +71,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1
 
 /* allow to overwrite serial and ethaddr */
@@ -139,8 +142,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x9c000000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x9c400000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
 
 #define CONFIG_SYS_HZ			1000
@@ -187,11 +188,12 @@
 
 #undef CONFIG_SYS_SKIP_DRAM_SCRUB
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * NAND Flash
  */
-#define CONFIG_NEW_NAND_CODE
 #define CONFIG_SYS_NAND0_BASE		0x0
 #undef CONFIG_SYS_NAND1_BASE
 
@@ -225,13 +227,6 @@
 #define CONFIG_MTD_DEBUG
 #define CONFIG_MTD_DEBUG_VERBOSE 1
 
-#define ADDR_COLUMN		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS		1
-
 #define CONFIG_SYS_NO_FLASH		1
 
 #define CONFIG_ENV_IS_IN_NAND	1