X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fzylonite.h;h=05000429b6501f27561497e4471f078cdb18422d;hb=2419169f5749d7af501b3b77a5336d1d535320de;hp=47ce15d0e01c780517117d74b3bf4683bac3f8d2;hpb=51bfee192099206a4397f15f3b93516e01f58ab0;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 47ce15d..0500042 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -41,17 +41,20 @@ #ifdef CONFIG_LCD #define CONFIG_SHARP_LM8V31 #endif -/* #define CONFIG_MMC 1 */ +#undef CONFIG_MMC #define BOARD_LATE_INIT 1 #undef CONFIG_SKIP_RELOCATE_UBOOT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* * Hardware drivers @@ -69,6 +72,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* allow to overwrite serial and ethaddr */ @@ -94,7 +98,7 @@ #ifdef TURN_ON_ETHERNET #define CONFIG_CMD_PING #else - #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #undef CONFIG_CMD_NET @@ -121,38 +125,40 @@ /* * Miscellaneous configurable options */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0x9c000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */ -#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ -#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ +#define CONFIG_SYS_HZ 1000 /* Monahans Core Frequency */ -#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ -#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ +#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ +#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* #define CFG_MMC_BASE 0xF0000000 */ +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes @@ -178,26 +184,25 @@ #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ -#define CFG_DRAM_BASE 0x80000000 /* at CS0 */ -#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ +#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */ -#undef CFG_SKIP_DRAM_SCRUB +#undef CONFIG_SYS_SKIP_DRAM_SCRUB /* * NAND Flash */ -#define CONFIG_NEW_NAND_CODE -#define CFG_NAND0_BASE 0x0 -#undef CFG_NAND1_BASE +#define CONFIG_SYS_NAND0_BASE 0x0 +#undef CONFIG_SYS_NAND1_BASE -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ /* nand timeout values */ -#define CFG_NAND_PROG_ERASE_TO 3000 -#define CFG_NAND_OTHER_TO 100 -#define CFG_NAND_SENDCMD_RETRY 3 +#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000 +#define CONFIG_SYS_NAND_OTHER_TO 100 +#define CONFIG_SYS_NAND_SENDCMD_RETRY 3 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ /* NAND Timing Parameters (in ns) */ @@ -214,27 +219,19 @@ #define NAND_TIMING_tAR 10 /* NAND debugging */ -#define CFG_DFC_DEBUG1 /* usefull */ -#undef CFG_DFC_DEBUG2 /* noisy */ -#undef CFG_DFC_DEBUG3 /* extremly noisy */ +#define CONFIG_SYS_DFC_DEBUG1 /* usefull */ +#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */ +#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */ #define CONFIG_MTD_DEBUG #define CONFIG_MTD_DEBUG_VERBOSE 1 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH 1 #define CONFIG_ENV_IS_IN_NAND 1 -#define CFG_ENV_OFFSET 0x40000 -#define CFG_ENV_OFFSET_REDUND 0x44000 -#define CFG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_OFFSET_REDUND 0x44000 +#define CONFIG_ENV_SIZE 0x4000 #endif /* __CONFIG_H */