X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fyucca.h;h=6417ed891df4e9693a1fe89e648639ce98cd6c1d;hb=afbc526336447a7357e9c82852df0377d09a8089;hp=95de1ea0a64684e2f2c9a6a5b54fb21949467bff;hpb=6c5879f380be38d85fef0d3aba3353358f4b2ff4;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 95de1ea..92d45d0 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -31,10 +31,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define DEBUG -#undef DEBUG - -#define CONFIG_IDENT_STRING "\nU_440SPe_V1R01 level06" /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ @@ -42,39 +38,52 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define EXTCLK_33_33 33333333 #define EXTCLK_66_66 66666666 #define EXTCLK_50 50000000 #define EXTCLK_83 83333333 -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME yucca +#include "amcc-common.h" + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS -#undef ENABLE_ECC + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */ - +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE -/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */ -/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */ -/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */ +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 + +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) #define CFG_FPGA_BASE 0xe2000000 /* epld */ #define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ @@ -93,39 +102,26 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CFG_EXT_SERIAL_CLOCK /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */ -#define IIC0_DIMM0_ADDR 0x53 -#define IIC0_DIMM1_ADDR 0x52 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#define CONFIG_DDR_ECC 1 /* with ECC support */ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define IIC0_BOOTPROM_ADDR 0x50 #define IIC0_ALT_BOOTPROM_ADDR 0x54 @@ -133,7 +129,7 @@ /* Don't probe these addrs */ #define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} -/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ +/* #if defined(CONFIG_CMD_EEPROM) */ /* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* #endif */ @@ -143,99 +139,37 @@ *----------------------------------------------------------------------*/ /* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */ -#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ +#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ +#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ #define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=/dev/nfs rw" -#define CONFIG_BOOTCOMMAND "bootm E7C00000" /* autoboot command */ -#define CONFIG_BOOTDELAY -1 /* -1 to disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#undef CONFIG_NET_MULTI -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -#define CONFIG_HAS_ETH0 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.80.10 -#define CONFIG_ETHADDR 00:04:AC:01:CA:FE -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SERVERIP 192.168.1.1 - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "loads_echo=1\0" \ - "netdev=eth0\0" \ - "hostname=yucca\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk-4.0/ppc_4xx\0" \ - "bootfile=yucca/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=E7F10000\0" \ "ramdisk_addr=E7F20000\0" \ - "load=tftp 100000 yuca/u-boot.bin\0" \ - "update=protect off 2:4-7;era 2:4-7;" \ - "cp.b ${fileaddr} fffc0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:EP:EP\0" \ "" -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - /* - * Miscellaneous configurable options + * Commands additional to the ones defined in amcc-common.h */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM -#define CFG_HZ 1 /* decrementer freq: 1 ms ticks */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ /*----------------------------------------------------------------------- * FLASH related @@ -254,12 +188,12 @@ #define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */ #define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/ -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR 0xfffa0000 -/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */ -#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ -#endif /* CFG_ENV_IS_IN_FLASH */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR 0xfffa0000 +/* #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */ +#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */ +#endif /* CONFIG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -267,11 +201,10 @@ /* General PCI */ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW i /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT @@ -284,33 +217,6 @@ */ /* Support for Intel 82557/82559/82559ER chips. */ #define CONFIG_EEPRO100 -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif /* FB Divisor selection */ #define FPGA_FB_DIV_6 6 @@ -498,8 +404,8 @@ #define FPGA_REG1C_PE1_WAKE 0x0040 #define FPGA_REG1C_PE2_WAKE 0x0020 #define FPGA_REG1C_PE0_PERST 0x0010 -#define FPGA_REG1C_PE1_PERST 0x0080 -#define FPGA_REG1C_PE2_PERST 0x0040 +#define FPGA_REG1C_PE1_PERST 0x0008 +#define FPGA_REG1C_PE2_PERST 0x0004 /*----------------------------------------------------------------------------+ | Defines @@ -513,6 +419,4 @@ #define PERIOD_33_33MHZ 30000 /* 30ns */ #define PERIOD_25_00MHZ 40000 /* 40ns */ -/*---------------------------------------------------------------------------*/ - #endif /* __CONFIG_H */