X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fxtfpga.h;h=9655b666eda71a4ae354ee712b15c3649c51c9e4;hb=78f67f11a9920ef988cbff5341616695c3e87ebd;hp=3e4b7cb00b58a8d63bedfef361492500ecc09ab2;hpb=e8f80a5a58c9b506453cc0780687e8ed457d30a6;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 3e4b7cb..9655b66 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -16,27 +16,18 @@ * differences. */ -/*=====================*/ -/* Board and Processor */ -/*=====================*/ - -#define CONFIG_XTFPGA - -/* FPGA CPU freq after init */ -#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) - /*===================*/ /* RAM Layout */ /*===================*/ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_SYS_MEMORY_BASE \ +#define CFG_SYS_MEMORY_BASE \ (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) -#define CONFIG_SYS_IO_BASE 0xf0000000 +#define CFG_SYS_IO_BASE 0xf0000000 #else -#define CONFIG_SYS_MEMORY_BASE 0x60000000 -#define CONFIG_SYS_IO_BASE 0x90000000 -#define CONFIG_MAX_MEM_MAPPED 0x10000000 +#define CFG_SYS_MEMORY_BASE 0x60000000 +#define CFG_SYS_IO_BASE 0x90000000 +#define CFG_MAX_MEM_MAPPED 0x10000000 #endif /* Onboard RAM sizes: @@ -51,78 +42,35 @@ */ #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE #else -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 #endif -#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) +#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000) /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ -#ifdef CONFIG_XTFPGA_LX60 -# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ -#else -# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ -#endif - -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ - -/* Linux boot param area in RAM (used only when booting linux) */ -#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) /* Memory test is destructive so default must not overlap vectors or U-Boot*/ -#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) -#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) - -/* Load address for stand-alone applications. - * MEMADDR cannot be used here, because the definition needs to be - * a plain number as it's used as -Ttext argument for ld in standalone - * example makefile. - * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. - */ -#if XCHAL_HAVE_PTP_MMU -#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR -#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 -#endif -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 -#endif -#if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED +#if defined(CFG_MAX_MEM_MAPPED) && \ + CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE +#define XTENSA_SYS_TEXT_ADDR \ + (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else -#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE -#endif - #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) - -/* Used by tftpboot; env var 'loadaddr' */ -#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) + (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) +#endif /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#define CONFIG_BOARD_POSTCLK_INIT -#define CONFIG_MISC_INIT_R - -#define CONFIG_BOOTFILE "uImage" /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*==============================*/ /* U-Boot autoboot configuration */ /*==============================*/ -#define CONFIG_MX_CYCLIC -#define CONFIG_SHOW_BOOT_PROGRESS - /*=========================================*/ /* FPGA Registers (board info and control) */ @@ -135,29 +83,17 @@ * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. */ -/* Date of FPGA bitstream build in binary coded decimal (BCD) */ -#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) -#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ -#define FPGAREG_MTH_WIDTH 8 -#define FPGAREG_MTH_MASK 0xFF000000 -#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ -#define FPGAREG_DAY_WIDTH 8 -#define FPGAREG_DAY_MASK 0x00FF0000 -#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ -#define FPGAREG_YEAR_WIDTH 16 -#define FPGAREG_YEAR_MASK 0x0000FFFF - /* FPGA core clock frequency in Hz (also input to UART) */ -#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ +#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ /* * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): * Bits 0..5 set the lower 6 bits of the default ethernet MAC. * Bit 6 is reserved for future use by Tensilica. - * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to * the base of flash * (when on/1) or to the base of RAM (when off/0). */ -#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ #define FPGAREG_MAC_WIDTH 6 #define FPGAREG_MAC_MASK 0x3f @@ -168,69 +104,49 @@ #define FPGAREG_BOOT_FLASH (1<