X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fwork_92105.h;h=f1a7853a80e66de881bdd2c6338ce2e27d8672ab;hb=605bc145f91d2a28ba2e517cae4e53e255e34b6f;hp=93c8d64b147bf8dcafc24236375a9d5ee50b0b60;hpb=1bccb23b7bb67e029cc6b22bf7d25243ef71c43c;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 93c8d64..f1a7853 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -14,128 +14,55 @@ #include /* - * Define work_92105 machine type by hand -- done only for compatibility - * with original board code - */ -#define CONFIG_MACH_TYPE 736 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* * Memory configurations */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - - GENERATED_GBL_DATA_SIZE) - -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ - -/* - * Ethernet Driver - */ - -#define CONFIG_LPC32XX_ETH -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ - -/* - * I2C driver - */ - -#define CONFIG_SYS_I2C_LPC32XX -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 350000 - -/* - * I2C EEPROM - */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * I2C RTC - */ - -#define CONFIG_RTC_DS1374 +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M /* * U-Boot General Configurations */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * NAND chip timings for FIXME: which one? */ -#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 -#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 -#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 -#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 -#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 -#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 -#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 +#define CFG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 +#define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 +#define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 +#define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 +#define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 +#define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000 +#define CFG_LPC32XX_NAND_MLC_WR_LOW 83333333 /* * NAND */ /* driver configuration */ -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_MAX_NAND_CHIPS 1 -#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE -#define CONFIG_NAND_LPC32XX_MLC +#define CFG_SYS_MAX_NAND_CHIPS 1 +#define CFG_SYS_NAND_BASE MLC_NAND_BASE /* * GPIO */ -#define CONFIG_LPC32XX_GPIO - /* * Environment */ /* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 - -/* * SPL */ /* SPL will be executed at offset 0 */ /* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 /* Use the framework and generic lib */ /* SPL will use serial */ /* SPL will load U-Boot from NAND offset 0x40000 */ -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 -#define CONFIG_SPL_PAD_TO 0x20000 -/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */ +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE /* * Include SoC specific configuration