X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fwork_92105.h;h=f1a7853a80e66de881bdd2c6338ce2e27d8672ab;hb=4db386655a889b6466d2c3f40839ad21205c6d21;hp=332453759791e4300796ee3d92147a152f8fd6e0;hpb=4de720e98d552dfda9278516bf788c4a73b3e56f;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 3324537..f1a7853 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -16,40 +16,32 @@
 /*
  * Memory configurations
  */
-#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
-
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_512K \
-					 - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_RTC_DS1374
+#define CFG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_128M
 
 /*
  * U-Boot General Configurations
  */
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 /*
  * NAND chip timings for FIXME: which one?
  */
 
-#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
-#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
-#define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
-#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
-#define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
-#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
-#define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333
+#define CFG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
+#define CFG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
+#define CFG_LPC32XX_NAND_MLC_NAND_TA      18181818
+#define CFG_LPC32XX_NAND_MLC_RD_HIGH      31250000
+#define CFG_LPC32XX_NAND_MLC_RD_LOW       45454545
+#define CFG_LPC32XX_NAND_MLC_WR_HIGH      40000000
+#define CFG_LPC32XX_NAND_MLC_WR_LOW       83333333
 
 /*
  * NAND
  */
 
 /* driver configuration */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
-#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
+#define CFG_SYS_MAX_NAND_CHIPS 1
+#define CFG_SYS_NAND_BASE MLC_NAND_BASE
 
 /*
  * GPIO
@@ -65,15 +57,12 @@
 
 /* SPL will be executed at offset 0 */
 /* SPL will use SRAM as stack */
-#define CONFIG_SPL_STACK     0x0000FFF8
 /* Use the framework and generic lib */
 /* SPL will use serial */
 /* SPL will load U-Boot from NAND offset 0x40000 */
-#define CONFIG_SPL_PAD_TO 0x20000
-/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE
+/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST   CONFIG_TEXT_BASE
 
 /*
  * Include SoC specific configuration