X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fvme8349.h;h=1c3430d849183161bb56252d066b50751b8d29aa;hb=42c9a494f1659db6043f980d5f4fdee86fdf9dfb;hp=14a84fabc97e86f000512be5bc3da9e5189a073a;hpb=8a81bfd271f9122933c865c790780024f5e2d576;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 14a84fa..1c3430d 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
@@ -97,14 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
 
 /*