X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fvision2.h;h=4744d7cb68bc40e6d4b612a0231908b9f30d601e;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=d95c0ba444cc060ade2d4ae82d376ac33bc5a9e1;hpb=97d7ab8a8eb6dbf7c9e8096f31031dfed81db8f8;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index d95c0ba..4744d7c 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -5,20 +5,7 @@
  *
  * Configuration settings for the MX51-3Stack Freescale board.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -30,29 +17,29 @@
 
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
 
+#ifndef MACH_TYPE_TTC_VISION2
+#define MACH_TYPE_TTC_VISION2	2775
+#endif
 #define CONFIG_MACH_TYPE	MACH_TYPE_TTC_VISION2
 
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN		(2048 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 /*
  * Hardware drivers
  */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX51_UART3
+#define CONFIG_MXC_UART_BASE	UART3_BASE
 #define CONFIG_MXC_GPIO
 #define CONFIG_MXC_SPI
 #define CONFIG_HW_WATCHDOG
@@ -70,7 +57,7 @@
  * Use gpio 4 pin 25 as chip select for SPI flash
  * This corresponds to gpio 121
  */
-#define CONFIG_SPI_FLASH_CS	(1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_CS	(1 | (121 << 8))
 #define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED  25000000
 
@@ -87,12 +74,15 @@
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 
 /* PMIC Controller */
-#define CONFIG_FSL_PMIC
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
 #define CONFIG_FSL_PMIC_BUS	0
 #define CONFIG_FSL_PMIC_CS	0
 #define CONFIG_FSL_PMIC_CLK	2500000
 #define CONFIG_FSL_PMIC_MODE	SPI_MODE_0
-#define CONFIG_RTC_MC13783
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
 
 /*
  * MMC Configs
@@ -116,9 +106,7 @@
  * Eth Configs
  */
 #define CONFIG_HAS_ETH1
-#define CONFIG_NET_MULTI
 #define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
 
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE				FEC_BASE_ADDR
@@ -132,7 +120,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX			3
 #define CONFIG_BAUDRATE				115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
 /***********************************************************
  * Command definition
@@ -173,12 +160,6 @@
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_HUSH_PARSER
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"Vision II U-boot > "
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
 
 /*
  * Physical Memory Map
@@ -188,19 +169,21 @@
 #define PHYS_SDRAM_1_SIZE		(256 * 1024 * 1024)
 #define PHYS_SDRAM_2			CSD1_BASE_ADDR
 #define PHYS_SDRAM_2_SIZE		(256 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE		0x90000000
-#define CONFIG_SYS_INIT_RAM_ADDR	0x1FFE8000
-
-#define CONFIG_SYS_INIT_RAM_SIZE		(64 * 1024)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					CONFIG_SYS_GBL_DATA_OFFSET)
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH
 
@@ -208,14 +191,16 @@
  * Framebuffer and LCD
  */
 #define CONFIG_PREBOOT
-#define CONFIG_LCD
-#define CONFIG_VIDEO_MX5
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define LCD_BPP		LCD_COLOR16
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
+#define CONFIG_IPUV3_CLK	133000000
 
 #endif				/* __CONFIG_H */