X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftuge1.h;h=81e11d2236117cf1cb312caf7fd61ed5fa16ef77;hb=73df96a38e693312bc2d5b565bc439f3b98e63ea;hp=1cd0985dc29753a05cbf8eeb67d232726a825552;hpb=fb1b099f109826532f589a152c7cdf418090e5f8;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 1cd0985..81e11d2 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -46,19 +46,6 @@ #define CONFIG_83XX_PCICLK 66000000 /* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - -/* * DDR Setup */ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ @@ -113,18 +100,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -133,18 +108,7 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + /* * Serial Port @@ -232,61 +196,6 @@ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* * Internal Definitions */ #define BOOTFLASH_START 0xF0000000 @@ -323,28 +232,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ @@ -413,14 +300,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ @@ -439,53 +318,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* - * Configuration for C2 on the local bus - */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) - -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #endif /* __CONFIG_H */