X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftrizepsiv.h;h=b4ec8f0c3cc187763aa776b4aa4a7cea7aaa79f5;hb=219f4788d33b04e394d4ade1feaedc0292acc790;hp=6367f873ef94414c5273d675abba39d133fc9e8a;hpb=28ac6719108e989429de2b3dfa90312ba7c4d27b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 6367f87..b4ec8f0 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -40,22 +40,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ - -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ +#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */ #define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_TEXT_BASE 0x0 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_DCACHE_OFF + #define RTC /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * Hardware drivers @@ -64,6 +65,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_SERIAL_MULTI #define CONFIG_FFUART 1 /* we use FFUART on Conxs */ #define CONFIG_BTUART 1 /* we use BTUART on Conxs */ @@ -81,7 +83,6 @@ */ #include -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_IMLS #define CONFIG_CMD_PING @@ -148,35 +149,33 @@ /* * Miscellaneous configurable options */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ -#define CFG_MMC_BASE 0xF0000000 +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes @@ -204,118 +203,140 @@ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_DRAM_BASE 0xa0000000 +#define CONFIG_SYS_DRAM_SIZE 0x04000000 -#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) /* * GPIO settings */ -#define CFG_GPSR0_VAL 0x00018000 -#define CFG_GPSR1_VAL 0x00000000 -#define CFG_GPSR2_VAL 0x400dc000 -#define CFG_GPSR3_VAL 0x00000000 -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPCR3_VAL 0x00000000 -#define CFG_GPDR0_VAL 0x00018000 -#define CFG_GPDR1_VAL 0x00028801 -#define CFG_GPDR2_VAL 0x520dc000 -#define CFG_GPDR3_VAL 0x0001E000 -#define CFG_GAFR0_L_VAL 0x801c0000 -#define CFG_GAFR0_U_VAL 0x00000013 -#define CFG_GAFR1_L_VAL 0x6990100A -#define CFG_GAFR1_U_VAL 0x00000008 -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x010900F2 -#define CFG_GAFR3_L_VAL 0x54000003 -#define CFG_GAFR3_U_VAL 0x00002401 -#define CFG_GRER0_VAL 0x00000000 -#define CFG_GRER1_VAL 0x00000000 -#define CFG_GRER2_VAL 0x00000000 -#define CFG_GRER3_VAL 0x00000000 -#define CFG_GFER0_VAL 0x00000000 -#define CFG_GFER1_VAL 0x00000000 -#define CFG_GFER2_VAL 0x00000000 -#define CFG_GFER3_VAL 0x00000020 - - -#define CFG_PSSR_VAL 0x20 /* CHECK */ +#define CONFIG_SYS_GPSR0_VAL 0x00018000 +#define CONFIG_SYS_GPSR1_VAL 0x00000000 +#define CONFIG_SYS_GPSR2_VAL 0x400dc000 +#define CONFIG_SYS_GPSR3_VAL 0x00000000 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0x00018000 +#define CONFIG_SYS_GPDR1_VAL 0x00028801 +#define CONFIG_SYS_GPDR2_VAL 0x520dc000 +#define CONFIG_SYS_GPDR3_VAL 0x0001E000 +#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000 +#define CONFIG_SYS_GAFR0_U_VAL 0x00000013 +#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A +#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 +#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 +#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000003 +#define CONFIG_SYS_GAFR3_U_VAL 0x00002401 +#define CONFIG_SYS_GRER0_VAL 0x00000000 +#define CONFIG_SYS_GRER1_VAL 0x00000000 +#define CONFIG_SYS_GRER2_VAL 0x00000000 +#define CONFIG_SYS_GRER3_VAL 0x00000000 + +#define CONFIG_SYS_GFER1_VAL 0x00000000 +#define CONFIG_SYS_GFER3_VAL 0x00000020 + +#if CONFIG_POLARIS +#define CONFIG_SYS_GFER0_VAL 0x00000001 +#define CONFIG_SYS_GFER2_VAL 0x00200000 +#else +#define CONFIG_SYS_GFER0_VAL 0x00000000 +#define CONFIG_SYS_GFER2_VAL 0x00000000 +#endif + +#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ /* * Clock settings */ -#define CFG_CKEN 0x01FFFFFF /* CHECK */ -#define CFG_CCCR 0x02000290 /* 520Mhz */ +#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */ +#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */ /* * Memory settings */ -#define CFG_MSC0_VAL 0x4df84df0 -#define CFG_MSC1_VAL 0x7ff87ff4 -#define CFG_MSC2_VAL 0xa26936d4 -#define CFG_MDCNFG_VAL 0x880009C9 -#define CFG_MDREFR_VAL 0x20ca201e -#define CFG_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_MSC0_VAL 0x4df84df0 +#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4 +#if CONFIG_POLARIS +#define CONFIG_SYS_MSC2_VAL 0xa2697ff8 +#else +#define CONFIG_SYS_MSC2_VAL 0xa26936d4 +#endif +#define CONFIG_SYS_MDCNFG_VAL 0x880009C9 +#define CONFIG_SYS_MDREFR_VAL 0x20ca201e +#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CFG_FLYCNFG_VAL 0x00000000 -#define CFG_SXCNFG_VAL 0x40044004 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 /* * PCMCIA and CF Interfaces */ -#define CFG_MECR_VAL 0x00000001 -#define CFG_MCMEM0_VAL 0x00004204 -#define CFG_MCMEM1_VAL 0x00010204 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00008407 -#define CFG_MCIO1_VAL 0x0000c108 +#define CONFIG_SYS_MECR_VAL 0x00000001 +#define CONFIG_SYS_MCMEM0_VAL 0x00004204 +#define CONFIG_SYS_MCMEM1_VAL 0x00010204 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00010504 +#define CONFIG_SYS_MCIO0_VAL 0x00008407 +#define CONFIG_SYS_MCIO1_VAL 0x0000c108 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000000 + +#if CONFIG_POLARIS +#define CONFIG_DM9000_BASE 0x0C800000 +#else +#define CONFIG_DM9000_BASE 0x08000000 +#endif + #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) #define CONFIG_USB_OHCI_NEW 1 -#define CFG_USB_OHCI_BOARD_INIT 1 -#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 -#define CFG_USB_OHCI_REGS_BASE 0x4C000000 -#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv" #define CONFIG_USB_STORAGE 1 -#define CFG_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 /* * FLASH and environment organization */ -#define CFG_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x40000 +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ /* write flash less slowly */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +/* Unlock to be used with Intel chips */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Flash environment locations */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ +#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* __CONFIG_H */