X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftricorder.h;h=80985a2655a180f223bdb11fcb72201beaf8a226;hb=3e1fa221f94b7ae3389d166882b77f1da5895f22;hp=087c44ca513f4e89130b45528ec1abb143bc4178;hpb=890880583d84607e36b52a785a96b167728bbf73;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 087c44c..80985a2 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -39,6 +39,9 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
 /* Clock Defines */
 #define V_OSCK				26000000 /* Clock output from T2 */
 #define V_SCLK				(V_OSCK >> 1)
@@ -60,6 +63,23 @@
 /* GPIO support */
 #define CONFIG_OMAP_GPIO
 
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2		/* GPIO32..63 are in GPIO bank 2 */
+
+/* LED support */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_CMD_LED			/* LED command */
+#define STATUS_LED_BIT			(1 << 0)
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1			(1 << 1)
+#define STATUS_LED_STATE1		STATUS_LED_ON
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2			(1 << 2)
+#define STATUS_LED_STATE2		STATUS_LED_ON
+#define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)
+
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
@@ -81,11 +101,11 @@
 #define CONFIG_DOS_PARTITION
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+ 
 
 /* EEPROM */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -117,12 +137,11 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-#define CONFIG_NAND_OMAP_BCH8
 #define CONFIG_BCH
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
 
 /* commands to include */
 #include <config_cmd_default.h>
@@ -151,7 +170,7 @@
 
 /* Environment information (this is the common part) */
 
-#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTDELAY		0
 
 /* hang() the board on panic() */
 #define CONFIG_PANIC_HANG
@@ -243,9 +262,10 @@
 	"loaduimage_ubi=ubi part ubi; " \
 		"ubifsmount ubi:root; " \
 		"ubifsload ${loadaddr} /boot/uImage\0" \
+	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"run loaduimage_ubi; " \
+		"run loaduimage_nand; " \
 		"bootm ${loadaddr}\0" \
 	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 			"if run loadbootscript; then " \
@@ -275,9 +295,9 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x00000000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
-					0x01000000) /* 16MB */
+					0x07000000) /* 112 MB */
 
 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
 
@@ -288,7 +308,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
@@ -336,7 +355,7 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		(55 * 1024)	/* 7 KB for stack */
+#define CONFIG_SPL_MAX_SIZE		(57 * 1024)	/* 7 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
@@ -349,14 +368,16 @@
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{12, 13, 14, 15, 16, 17, 18, 19, 20,\
-			21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
-			34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
-			47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
-			60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					 52, 53, 54, 55, 56}
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 
@@ -366,4 +387,6 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
 
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x81000000
 #endif /* __CONFIG_H */