X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fti816x_evm.h;h=1aca83a9bcebe776d06b691ce0275ebe13278eb3;hb=898bd53e6a930080cee7cd7b1a09120c4dfd9467;hp=cffa79416f9014e1b5912b554541a9ec0b5f1c96;hpb=8bef03683623d6a7adfff1f859ed44fad9e92ed7;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index cffa794..1aca83a 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -13,14 +13,7 @@
 #include <asm/arch/omap.h>
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
-	DEFAULT_LINUX_BOOT_ENV \
-	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-
-#define CONFIG_BOOTCOMMAND			\
-	"mmc rescan;"				\
-	"fatload mmc 0 ${loadaddr} uImage;"	\
-	"bootm ${loadaddr}"			\
+	DEFAULT_LINUX_BOOT_ENV
 
 /* Clock Defines */
 #define V_OSCK          24000000    /* Clock output from T2 */
@@ -32,9 +25,7 @@
 /**
  * Platform/Board specific defs
  */
-#define CONFIG_SYS_CLK_FREQ     27000000
 #define CONFIG_SYS_TIMERBASE    0x4802E000
-#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
 
 /*
  * NS16550 Configuration
@@ -57,14 +48,7 @@
 /* NAND: SPL related configs */
 
 /* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
-					 CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
 #define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
@@ -75,28 +59,8 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
-#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 
 /* SPL */
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
-					 CONFIG_SPL_TEXT_BASE)
-
-#define CONFIG_NET_RETRY_COUNT	10
-
-/* Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
 
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_TIMER
-#endif
 #endif