X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra30-common.h;h=c2096fbe7ec497660f062bdc56498acbe364f1de;hb=19d1f1a2f3ccfbf85125150f7876ce22714b38bd;hp=b5550d7d099c74bed362573f003e478196eb35f9;hpb=d627eefcd5e72db00889718ca9ee1dcb4d026fc9;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index b5550d7..c2096fb 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -9,38 +9,20 @@
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * Errata configuration
- */
-#define CONFIG_ARM_ERRATA_743622
-#define CONFIG_ARM_ERRATA_751472
-
 /*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
 /*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
-
-/*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
 #define CONFIG_STACKBASE	0x82800000	/* 40MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x8010E000
+#define CONFIG_SYS_TEXT_BASE	0x80110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -48,6 +30,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -63,9 +48,11 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#define CONFIG_LOADADDR 0x81000000
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
-	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
 
@@ -74,9 +61,6 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
 #define CONFIG_SPL_STACK		0x800ffffc
 
-/* Total I2C ports on Tegra30 */
-#define TEGRA_I2C_NUM_CONTROLLERS	5
-
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10