X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra30-common.h;h=baf3d00f34ba5272937ac657fed3339506791507;hb=c6b968da78ce3fa7224c0ddf15fe170c7c05b27e;hp=04517e14092c59638fd2d30175f27173bd492918;hpb=a885f85214dcd358b29a2ffe69ab4f9b515b95e9;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 04517e1..baf3d00 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -2,23 +2,7 @@
  *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _TEGRA30_COMMON_H_
@@ -26,28 +10,25 @@
 #include "tegra-common.h"
 
 /*
- * NS16550 Configuration
+ * Errata configuration
  */
-#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
 
 /*
- * High Level Configuration Options
+ * NS16550 Configuration
  */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
 #define CONFIG_STACKBASE	0x82800000	/* 40MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x8010E000
+#define CONFIG_SYS_TEXT_BASE	0x80110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -55,6 +36,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -70,9 +54,11 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#define CONFIG_LOADADDR 0x81000000
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
-	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
 
@@ -81,9 +67,9 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
 #define CONFIG_SPL_STACK		0x800ffffc
 
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra30/u-boot-spl.lds"
-
-/* Total I2C ports on Tegra30 */
-#define TEGRA_I2C_NUM_CONTROLLERS	5
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA30_COMMON_H_ */