X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra20-common.h;h=fdd89969554150ba235d2a34bd20d7f47f9ad91e;hb=b11f634b1c1be6ab419758c6596c673445e5ac70;hp=0841f33bfc9e968b386d0daad1f08fc655e08142;hpb=48cfca240db06b2945f23b44e37b9a6018cd40fa;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 0841f33..fdd8996 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -1,24 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _TEGRA20_COMMON_H_
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * Errata configuration
- */
-#define CONFIG_ARM_ERRATA_716044
-#define CONFIG_ARM_ERRATA_742230
-#define CONFIG_ARM_ERRATA_751472
-
 /*
  * NS16550 Configuration
  */
@@ -27,12 +16,11 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_STACKBASE	0x02800000	/* 40MB */
+#define CONFIG_STACKBASE	0x03800000	/* 56MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x0010E000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -49,13 +37,13 @@
  *   should not overlap that area, or the kernel will have to copy itself
  *   somewhere else before decompression. Similarly, the address of any other
  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
- *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
  *   compressed load address.
  *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- *   the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
  *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
 #define CONFIG_LOADADDR 0x01000000
@@ -63,11 +51,11 @@
 	"scriptaddr=0x10000000\0" \
 	"pxefile_addr_r=0x10100000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
-	"fdt_addr_r=0x02000000\0" \
-	"ramdisk_addr_r=0x02100000\0"
+	"fdtfile=" FDTFILE "\0" \
+	"fdt_addr_r=0x03000000\0" \
+	"ramdisk_addr_r=0x03100000\0"
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x00108000
 #define CONFIG_SYS_SPL_MALLOC_START	0x00090000
 #define CONFIG_SPL_STACK		0x000ffffc
 
@@ -90,9 +78,8 @@
  * parameter, the default (2) causes occasional Data Buffer Errors in OUT
  * packets depending on the buffer address and size.
  */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
 #define CONFIG_EHCI_IS_TDI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION