X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra20-common.h;h=793310ff473d3d119989688254262711c3667140;hb=b0cf733933c3bc1b4ab353e16affabc60f863db5;hp=21bf9771742424dcf4da509e8550a2964b585b0a;hpb=1cad23c5f471d695bed1e3907e30caee3c2a3056;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 21bf977..793310f 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -9,9 +9,6 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 /*
  * Errata configuration
  */
@@ -24,19 +21,15 @@
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
 
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
-
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR	0x00A00800	/* default */
 #define CONFIG_STACKBASE	0x02800000	/* 40MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x0010E000
+#define CONFIG_SYS_TEXT_BASE	0x00110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -62,10 +55,11 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#define CONFIG_LOADADDR 0x01000000
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x10000000\0" \
 	"pxefile_addr_r=0x10100000\0" \
-	"kernel_addr_r=0x01000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
 	"fdt_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0"
 
@@ -97,9 +91,6 @@
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
-/* Total I2C ports on Tegra20 */
-#define TEGRA_I2C_NUM_CONTROLLERS	4
-
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION