X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra20-common.h;h=71867bb6baac5c124fae1110311fb95d74f2121d;hb=46b5c8ed017958fc387ab86c71ae6c90abb6793c;hp=a2b14d8ead86d35b011766ec5f8a7c277706601a;hpb=52af0101be55da74a32e9b169864508101f886fe;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index a2b14d8..71867bb 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -69,12 +69,4 @@
 #define TEGRA_LP0_VEC
 #endif
 
-/*
- * This parameter affects a TXFILLTUNING field that controls how much data is
- * sent to the latency fifo before it is sent to the wire. Without this
- * parameter, the default (2) causes occasional Data Buffer Errors in OUT
- * packets depending on the buffer address and size.
- */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 #endif /* _TEGRA20_COMMON_H_ */