X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra20-common.h;h=617bfb2197cf9683d0fc7fb1e8f193f50e465f37;hb=218e2c45af83f2cb7b1374b9023b4ced6eb0bb77;hp=a2b14d8ead86d35b011766ec5f8a7c277706601a;hpb=8bbbd6337361cadad96b163bde4ae675752b7778;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index a2b14d8..617bfb2 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -54,11 +54,6 @@
 	"fdt_addr_r=0x03000000\0" \
 	"ramdisk_addr_r=0x03100000\0"
 
-/* Defines for SPL */
-
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
-
 #ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR			0x1C406000
 #define TEGRA_LP0_SIZE			0x2000
@@ -69,12 +64,4 @@
 #define TEGRA_LP0_VEC
 #endif
 
-/*
- * This parameter affects a TXFILLTUNING field that controls how much data is
- * sent to the latency fifo before it is sent to the wire. Without this
- * parameter, the default (2) causes occasional Data Buffer Errors in OUT
- * packets depending on the buffer address and size.
- */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 #endif /* _TEGRA20_COMMON_H_ */