X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra20-common.h;h=00e85c48c41bba41f136dad1f6f0e037a1aaabf5;hb=930c514d47a29e1f94a5b61fe965400a4f5635c3;hp=b009a316b14cd29e4389e64dfef8cbfec111bf3c;hpb=19d829fa60fc4e6df514a046142faaaf9fc8185d;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index b009a31..00e85c4 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -25,23 +25,14 @@
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
 
 /*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
-
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
-
-/*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR	0x00A00800	/* default */
 #define CONFIG_STACKBASE	0x02800000	/* 40MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x0010E000
+#define CONFIG_SYS_TEXT_BASE	0x00110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -49,6 +40,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -64,9 +58,11 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#define CONFIG_LOADADDR 0x01000000
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x10000000\0" \
-	"kernel_addr_r=0x01000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
 	"fdt_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0"
 
@@ -96,9 +92,7 @@
  */
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
 #define CONFIG_EHCI_IS_TDI
-
-/* Total I2C ports on Tegra20 */
-#define TEGRA_I2C_NUM_CONTROLLERS	4
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION