X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra124-common.h;h=b275f795a35eb607bc4a3c37f7b9eb51eda9af56;hb=d01806a8fcbdaedcc67cead56ece572021d97ab7;hp=f2b3774da8ff5c90394735faab4db308a9b34a1b;hpb=bd5053ffa5b8162257537bdb79ba829372423096;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index f2b3774..b275f79 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -1,8 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2013 * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA124_COMMON_H_ @@ -10,27 +9,19 @@ #include "tegra-common.h" -/* Cortex-A15 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 /* * Memory layout for where various images get loaded by boot scripts: @@ -56,10 +47,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" @@ -71,6 +63,8 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 + +/* GPU needs setup */ +#define CONFIG_TEGRA_GPU #endif /* _TEGRA124_COMMON_H_ */