X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra124-common.h;h=0eb8f92809181df96277df40dc084e28a8f544d0;hb=632fb978a513e22e4cbc8410156a185716216649;hp=0a4541bd20e6da5f7c9d808c481da63e0fed0444;hpb=d53ccdb341cf16e32c0ca2d6099b194d9572fe0c;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 0a4541b..0eb8f92 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2013
  * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #ifndef _TEGRA124_COMMON_H_
@@ -10,32 +9,19 @@
 
 #include "tegra-common.h"
 
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
 /*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124			/* is an NVIDIA Tegra124 core */
-
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
-
-/*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
-#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+#define CONFIG_STACKBASE	0x83800000	/* 56MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x8010E000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -52,32 +38,33 @@
  *   should not overlap that area, or the kernel will have to copy itself
  *   somewhere else before decompression. Similarly, the address of any other
  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
- *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
  *   compressed load address.
  *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- *   the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
  *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#define CONFIG_LOADADDR 0x81000000
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
 	"pxefile_addr_r=0x90100000\0" \
-	"kernel_addr_r=0x81000000\0" \
-	"fdt_addr_r=0x82000000\0" \
-	"ramdisk_addr_r=0x82100000\0"
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdtfile=" FDTFILE "\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"ramdisk_addr_r=0x83100000\0"
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x80108000
 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
 #define CONFIG_SPL_STACK		0x800ffffc
 
-/* Total I2C ports on Tegra124 */
-#define TEGRA_I2C_NUM_CONTROLLERS	5
-
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
 
+/* GPU needs setup */
+#define CONFIG_TEGRA_GPU
+
 #endif /* _TEGRA124_COMMON_H_ */