X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra114-common.h;h=ccfc516a825636184ea5d498f4e7e2837809f01c;hb=725e09b82392711a3bf9822a2d7449e1deba4865;hp=21454d47cb5f6935374757a02b6e5f94577c4b76;hpb=45fe3809b9923b92f221d70eb45ae071059fd5e0;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 21454d4..ccfc516 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -1,16 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _TEGRA114_COMMON_H_
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */
@@ -24,7 +20,6 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE	0x80110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -66,6 +61,5 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA114_COMMON_H_ */