X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftao3530.h;h=de44aa5cf76d433e5ba2ce50d77e415d506076bf;hb=8850c5d57c10aa6431d138d426e6e105c99cc7ba;hp=4d66dd2407b4f1724057823221092762f289f4b0;hpb=f4c6f9335c1e867862dcebcfa9c05b2e3dd05636;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 4d66dd2..de44aa5 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -13,33 +13,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ - -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -#define MACH_TYPE_OMAP3_TAO3530 2836 #define CONFIG_SDRC /* Has an SDRC controller */ #include /* get chip and board defs */ #include -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) @@ -78,18 +60,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ -#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ -#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ /* commands to include */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ @@ -101,7 +71,6 @@ #define CONFIG_CMD_NAND /* NAND support */ -#define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 @@ -111,7 +80,6 @@ /* * TWL4030 */ -#define CONFIG_TWL4030_POWER #define CONFIG_TWL4030_LED /* @@ -128,7 +96,6 @@ /* devices */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT /* Environment information */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ @@ -189,7 +156,6 @@ /* turn on command-line edit/hist/auto */ #define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY #define CONFIG_AUTO_COMPLETE /* Print Buffer Size */ @@ -218,13 +184,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ - -/* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ @@ -269,7 +228,7 @@ */ /* USB EHCI */ -#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 @@ -279,34 +238,20 @@ #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS -#define CONFIG_USB_STORAGE -#define CONGIG_CMD_STORAGE /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE @@ -329,7 +274,8 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) /* * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the