X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftao3530.h;h=c34e785d9e559d658937b603e772dc4f32db354f;hb=abf9e5d0f2cd123951dfae0d5605b54394721b97;hp=6e04e6b50922a9645e2d8bd90cba9d162a33166f;hpb=ebca902aeb3af3eaedd2787928184ad84a86b98f;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 6e04e6b..c34e785 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Configuration settings for the TechNexion TAO-3530 SOM * equipped on Thunder baseboard. @@ -6,8 +7,6 @@ * Tapani Utriainen * * Copyright (C) 2013 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -24,8 +23,6 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_MISC_INIT_R - #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -35,7 +32,6 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ /* * Hardware drivers @@ -59,7 +55,6 @@ #define CONFIG_ENV_OVERWRITE /* commands to include */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_SYS_I2C #define CONFIG_I2C_MULTI_BUS @@ -67,13 +62,10 @@ /* * TWL4030 */ -#define CONFIG_TWL4030_LED /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ @@ -158,7 +150,6 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 @@ -178,7 +169,6 @@ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_OFFSET 0x260000 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 @@ -227,7 +217,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ CONFIG_SPL_TEXT_BASE)