X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ftaihu.h;h=4ebaf2e2a51ed865ec306a2c67e6a3117fc723c2;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=bcb8732a65b212422abc7f8f14a59f7e1c05a6ad;hpb=508eb85db7065e34948c189c83f7e348c1cfd61e;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/taihu.h b/include/configs/taihu.h index bcb8732..4ebaf2e 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -5,23 +5,7 @@ * (C) Copyright 2005-2007 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -32,6 +16,8 @@ #define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_TAIHU 1 /* on a taihu board */ +#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 + /* * Include common defines/options for all AMCC eval boards */ @@ -102,8 +88,8 @@ #define CONFIG_CMD_SPI #undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ -#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ -#define CFG_SDRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ +#define CONFIG_SYS_SDRAM_BANKS 2 /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -112,38 +98,37 @@ #define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ /* SDRAM timings used in datasheet */ -#define CFG_SDRAM_CL 3 /* CAS latency */ -#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ -#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ -#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ -#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ +#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ +#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ /* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. * The Linux BASE_BAUD define should match this configuration. * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE 1 +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CONFIG_SYS_BASE_BAUD 691200 /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #define CONFIG_SOFT_SPI #define SPI_SCL spi_scl @@ -159,7 +144,7 @@ unsigned char spi_read(void); /* standard dtt sensor configuration */ #define CONFIG_DTT_DS1775 1 #define CONFIG_DTT_SENSORS { 0 } -#define CFG_I2C_DTT_ADDR 0x49 +#define CONFIG_SYS_I2C_DTT_ADDR 0x49 /*----------------------------------------------------------------------- * PCI stuff @@ -170,44 +155,45 @@ unsigned char spi_read(void); #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ +#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ +#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ +#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ #define CONFIG_EEPRO100 1 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) */ -#define CFG_FLASH_BASE 0xFFE00000 +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_ADDR0 0x555 -#define CFG_FLASH_ADDR1 0x2aa -#define CFG_FLASH_WORD_SIZE unsigned short +#define CONFIG_SYS_FLASH_ADDR0 0x555 +#define CONFIG_SYS_FLASH_ADDR1 0x2aa +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ @@ -218,19 +204,19 @@ unsigned char spi_read(void); /*----------------------------------------------------------------------- * NVRAM organization */ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ #ifdef CONFIG_ENV_IS_IN_NVRAM #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ #define CONFIG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/ + (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/ #endif /*----------------------------------------------------------------------- * PPC405 GPIO Configuration */ -#define CFG_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ { \ /* GPIO Core 0 */ \ { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ @@ -274,48 +260,47 @@ unsigned char spi_read(void); * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory (OCM) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 +#define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ /* Memory Bank 0 (Flash/SRAM) initialization */ -#define CFG_EBC_PB0AP 0x03815600 -#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB0AP 0x03815600 +#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ /* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CFG_EBC_PB1AP 0x05815600 -#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB1AP 0x05815600 +#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ /* Memory Bank 2 (USB device) initialization */ -#define CFG_EBC_PB2AP 0x03016600 -#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB2AP 0x03016600 +#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 3 (LCM and D-flip-flop) initialization */ -#define CFG_EBC_PB3AP 0x158FF600 -#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB3AP 0x158FF600 +#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 4 (not install) initialization */ -#define CFG_EBC_PB4AP 0x158FF600 -#define CFG_EBC_PB4CR 0x5021A000 +#define CONFIG_SYS_EBC_PB4AP 0x158FF600 +#define CONFIG_SYS_EBC_PB4CR 0x5021A000 #define CPLD_REG0_ADDR 0x50100000 #define CPLD_REG1_ADDR 0x50100001