X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Ft3corp.h;h=964115f980c28350d4ccf9f8c4e625716a400fdf;hb=cb33bda44f4bbf6fb58adf41dced313ca38da6fc;hp=39ca7930baf81d537fe00ca5ed58c886ccd594e5;hpb=2e6e1772c0e34871769be4aef79748fe3e47d953;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 39ca793..964115f 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -2,20 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -29,7 +16,10 @@ */ #define CONFIG_460GT 1 /* Specific PPC460GT */ #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 +#endif #define CONFIG_HOSTNAME t3corp @@ -40,11 +30,9 @@ #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_FIT #define CFG_ALT_MEMTEST /* @@ -93,10 +81,9 @@ * Initial RAM & stack pointer (placed in OCM) */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* @@ -117,11 +104,16 @@ */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + (CONFIG_SYS_FPGA1_BASE + 0x01000000) } +#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \ + 0xbddf } /* set async read mode */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/ @@ -311,9 +303,8 @@ /* * I2C */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 @@ -352,12 +343,12 @@ "ramdisk_addr=fc200000\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ + "unlock=yes\0" \ "" /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM @@ -366,8 +357,7 @@ * PCI stuff */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_CONFIG_HOST_BRIDGE @@ -378,7 +368,6 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - /* * External Bus Controller (EBC) Setup */ @@ -420,7 +409,7 @@ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) @@ -437,7 +426,7 @@ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) @@ -454,7 +443,7 @@ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED)