X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsuvd3.h;h=d74707971ba473f75b3c78707c8372dde4c8c0f2;hb=6d7dacf726ca043a3f5487549bbfa506c990c813;hp=2a3f7ff52602c75e63e778fdb0f8dd4e5de360de;hpb=0e0674fcab819e829929716aa5aa0f10d7feb75a;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 2a3f7ff..d747079 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -20,77 +20,15 @@
  * High Level Configuration Options
  */
 
-/* This needs to be set prior to including km/km83xx-common.h */
-
 #define CONFIG_HOSTNAME		"suvd3"
-#define CONFIG_KM_BOARD_NAME   "suvd3"
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#define CONFIG_SYS_APP1_BASE		0xA0000000
-#define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
-#define CONFIG_SYS_APP2_BASE		0xB0000000
-#define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  2   Local   UPMA    16 bit  256MB APP1
- *  3   Local   GPCM    16 bit  256MB APP2
- *
- */
-
-/*
- * APP1 on the local bus CS2
- */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
-				 BR_PS_16 | \
-				 BR_MS_UPMA | \
-				 BR_V)
-#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 
-#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
-				 BR_PS_16 | \
-				 BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
-				 OR_GPCM_CSNT | \
-				 OR_GPCM_ACS_DIV4 | \
-				 OR_GPCM_SCY_3 | \
-				 OR_GPCM_TRLX_SET)
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
 
 #define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
 			 0x0000c000 | \
 			 MxMR_WLFx_2X)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
-
-/*
- * MMU Setup
- */
-/* APP1:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-
 #endif /* __CONFIG_H */