X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fstxssa.h;h=96d7128d0afe68ef0e56df31be243b56f7839402;hb=842033e6964e9e5d34aca893c1845416dd8ac2cc;hp=a1e9789ea01b512b1a1ea64c428ffc9f067c549e;hpb=1a5017601f6d17caedaa2bf069485d3e4155f1c0;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index a1e9789..96d7128 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -43,14 +43,13 @@ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ #define CONFIG_MPC8560 1 +#define CONFIG_SYS_TEXT_BASE 0xFFF80000 + #define CONFIG_PCI /* PCI ethernet support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -68,13 +67,12 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 /* Localbus connector. There are many options that can be @@ -82,115 +80,120 @@ * This address, however, is used to configure a 256M local bus * window that includes the Config latch below. */ -#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ -#define CFG_LBC_OPTION_SIZE 256 /* 256MB */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ +#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */ /* There are various flash options used, we configure for the largest, * which is 64Mbytes. The CFI works fine and will discover the proper * sizes. */ #ifdef CONFIG_STXSSA_4M -#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ +#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ #else -#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ #endif -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */ -#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7) +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */ +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7) -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CFG_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_PROTECTION /* The configuration latch is Chip Select 1. * It's an 8-bit latch in the lower 8 bits of the word. */ -#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */ -#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */ -#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ +#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */ +#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */ +#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif -#ifdef CFG_RAMBOOT -#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#ifdef CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ #endif -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -/* - * DDR Setup - */ +/* DDR Setup */ +#define CONFIG_FSL_DDR1 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD +#undef CONFIG_FSL_DDR_INTERACTIVE -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ #undef CONFIG_CLOCKS_IN_MHZ /* local bus definitions */ -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ -#define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ +#define CONFIG_SYS_OR2_PRELIM 0xfc006901 +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_SYS_LBC_LSRT 0x20000000 +#define CONFIG_SYS_LBC_MRTPR 0x20000000 +#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 +#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 +#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 +#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 +#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CFG_BAUDRATE_TABLE \ +#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -198,44 +201,42 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#undef CFG_I2C_NOPROBES -#define CFG_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#undef CONFIG_SYS_I2C_NOPROBES +#define CONFIG_SYS_I2C_OFFSET 0x3000 /* I2C RTC */ #define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* I2C EEPROM. AT24C32, we keep our environment in here. */ -#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 /* * Standard 8555 PCI mapping. * Addresses are mapped 1-1. */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe3000000 -#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ #if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_MPC85XX_PCI2 1 -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_EEPRO100 @@ -248,16 +249,12 @@ #endif #define CONFIG_PCI_SCAN_SHOW -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 @@ -286,13 +283,13 @@ * - Select bus for bd/buffers * - Full duplex */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 + #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CONFIG_SYS_CPMFCR_RAMTYPE 0 #if 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) + #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) #else - #define CFG_FCC_PSMR 0 + #define CONFIG_SYS_FCC_PSMR 0 #endif #define FETH2_RST 0x01 #elif (CONFIG_ETHER_INDEX == 3) @@ -309,24 +306,24 @@ /* Environment - default config is in flash, see below */ #if 0 /* in EEPROM */ -# define CFG_ENV_IS_IN_EEPROM 1 -# define CFG_ENV_OFFSET 0 -# define CFG_ENV_SIZE 2048 +# define CONFIG_ENV_IS_IN_EEPROM 1 +# define CONFIG_ENV_OFFSET 0 +# define CONFIG_ENV_SIZE 2048 #else /* in flash */ -# define CFG_ENV_IS_IN_FLASH 1 +# define CONFIG_ENV_IS_IN_FLASH 1 # ifdef CONFIG_STXSSA_4M -# define CFG_ENV_SECT_SIZE 0x20000 +# define CONFIG_ENV_SECT_SIZE 0x20000 # else /* default configuration - 64 MiB flash */ -# define CFG_ENV_SECT_SIZE 0x40000 +# define CONFIG_ENV_SECT_SIZE 0x40000 # endif -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x4000 -# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +# define CONFIG_ENV_SIZE 0x4000 +# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_TIMESTAMP /* Print image info with ts */ @@ -352,6 +349,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -361,8 +359,8 @@ #define CONFIG_CMD_MII #endif -#if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV +#if defined(CONFIG_SYS_RAMBOOT) + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #else #define CONFIG_CMD_ELF @@ -374,33 +372,25 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -422,7 +412,7 @@ * but only little space is available, so we use a very simple setup. * With environment in flash, we use a more powerful default configuration. */ -#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ +#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ #define CONFIG_BAUDRATE 38400 @@ -434,8 +424,8 @@ #define CONFIG_GATEWAYIP 192.168.85.1 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_HOSTNAME STX_SSA -#define CONFIG_ROOTPATH /gppproot -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH "/gppproot" +#define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x1000000 #else /* ENV IS IN FLASH -- use a full-blown envionment */ @@ -476,6 +466,6 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#endif /* CFG_ENV_IS_IN_EEPROM */ +#endif /* CONFIG_ENV_IS_IN_EEPROM */ #endif /* __CONFIG_H */