X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fstv0991.h;h=2f808c6c72daac3a699cbde0bb0d1ee3af8ca504;hb=f40574e2d78c96a3818c4fa2379382d924866a6e;hp=1526d13ac158ddf20bf3665f86df2fb1a52ce6bd;hpb=e573bdb324c78fac56655a493bea843842c9d9f8;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 1526d13..2f808c6 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -9,12 +9,9 @@
 #define __CONFIG_STV0991_H
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_SYS_CORTEX_R4
 
-#define CONFIG_SYS_NO_FLASH
-
 /* ram memory-related information */
 #define CONFIG_NR_DRAM_BANKS			1
 #define PHYS_SDRAM_1				0x00000000
@@ -31,7 +28,6 @@
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 16 * 1024)
 
 /* serial port (PL011) configuration */
-#define CONFIG_BAUDRATE				115200
 #define CONFIG_PL01X_SERIAL
 
 /* user interface */
@@ -45,7 +41,7 @@
 #define CONFIG_SYS_INIT_RAM_ADDR		0x00190000
 #define CONFIG_SYS_INIT_SP_OFFSET		\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* U-boot Load Address */
+/* U-Boot Load Address */
 #define CONFIG_SYS_TEXT_BASE			0x00010000
 #define CONFIG_SYS_INIT_SP_ADDR			\
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
@@ -53,39 +49,29 @@
 /* GMAC related configs */
 
 #define CONFIG_MII
-#define CONFIG_PHYLIB
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_PHY_MICREL
 
 /* Command support defines */
-#define CONFIG_CMD_PING
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 
 #define CONFIG_SYS_MEMTEST_START               0x0000
 #define CONFIG_SYS_MEMTEST_END                 1024*1024
-#define CONFIG_CMD_MEMTEST
 
 /* Misc configuration */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_BOOTDELAY                       3
 #define CONFIG_BOOTCOMMAND                     "go 0x40040000"
 
-#define CONFIG_OF_LIBFDT
-
 /*
 + * QSPI support
 + */
 #ifdef CONFIG_OF_CONTROL		/* QSPI is controlled via DT */
-#define CONFIG_CADENCE_QSPI
 #define CONFIG_CQSPI_DECODER		0
 #define CONFIG_CQSPI_REF_CLK		((30/4)/2)*1000*1000
-#define CONFIG_CMD_SPI
+#define CONFIG_BOUNCE_BUFFER
 
-#define CONFIG_SPI_FLASH_STMICRO	/* Micron/Numonyx flash */
-#define CONFIG_SPI_FLASH_WINBOND	/* WINBOND */
-#define CONFIG_CMD_SF
 #endif
 
 #endif /* __CONFIG_H */