X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fspieval.h;h=69d2d67ab1cdbfe4b45b66d682e48cfb7bc01e39;hb=29f8f58ff40c67f7f2e11afd1715173094e52ac2;hp=9ebb51e0ab77125e136e251fd7a2f9c4d2e4c6a4;hpb=cd65a3dc872407e6278062246a4eb5e10f180d7e;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 9ebb51e..69d2d67 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -44,10 +44,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration @@ -88,12 +85,6 @@ #define CONFIG_NS8382X 1 #endif /* CONFIG_STK52XX */ -#ifdef CONFIG_PCI -#define ADD_PCI_CMD CFG_CMD_PCI -#else -#define ADD_PCI_CMD 0 -#endif - /* * Video console */ @@ -110,12 +101,6 @@ #define CFG_CONSOLE_IS_IN_ENV #endif -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -124,10 +109,7 @@ /* USB */ #ifdef CONFIG_STK52XX #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif /* POST support */ @@ -136,43 +118,61 @@ CFG_POST_I2C) #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 #endif -/* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) -#else -#define ADD_IDE_CMD 0 -#endif /* - * Supported commands + * BOOTP options */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) + #define CONFIG_CMD_IDE + #define CONFIG_CMD_FAT + #define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_STK52XX + #define CONFIG_CMD_USB + #define CONFIG_CMD_FAT +#endif + +#ifdef CONFIG_VIDEO + #define CONFIG_CMD_BMP +#endif + +#ifdef CONFIG_PCI + #define CONFIG_CMD_PCI + #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 +#endif + +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -186,7 +186,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -219,17 +219,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -406,7 +406,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -425,9 +425,13 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW @@ -444,7 +448,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ @@ -452,32 +456,25 @@ #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF #define CONFIG_LAST_STAGE_INIT -#endif /* * SRAM - Do not map below 2 GB in address space, because this area is used * for SDRAM autosizing. */ -#if defined (CONFIG_CS_AUTOCONF) #define CFG_CS2_START 0xE5000000 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ #define CFG_CS2_CFG 0x0004D930 -#endif /* * Grafic controller - Do not map below 2 GB in address space, because this * area is used for SDRAM autosizing. */ -#if defined (CONFIG_CS_AUTOCONF) #define SM501_FB_BASE 0xE0000000 #define CFG_CS1_START (SM501_FB_BASE) #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ #define CFG_CS1_CFG 0x8F48FF70 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 -#endif #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */