X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsorcery.h;h=b4da4ce9206b565fe4292b0041c56a5b181ca5dc;hb=9314cee6917444ab88bd4e758da7a30975120187;hp=fe014eabcbc1c79d476d012b40ae775cdd83e02e;hpb=f2c2a937d8c4a44f63ff88bf82023e03a29497a2;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index fe014ea..b4da4ce 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -31,6 +31,8 @@
 #define CONFIG_MPC8220		1
 #define CONFIG_SORCERY		1	/* Sorcery board */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
 #define CFG_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
@@ -100,7 +102,7 @@
 #define CONFIG_HOSTNAME		sorcery
 
 #define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
 #undef	CONFIG_BOOTARGS
@@ -187,9 +189,9 @@
 #define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks */
 #define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST 	{ CFG_FLASH_BASE,  \
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE,  \
 				CFG_FLASH_BASE+0x04000000 } /* two banks */
 
 /*
@@ -205,13 +207,13 @@
 #define CONFIG_ENV_OVERWRITE	1
 
 #if defined CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_EEPROM
-#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_EEPROM
+#elif defined CONFIG_ENV_IS_IN_NVRAM
 #undef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_EEPROM
-#elif defined CFG_ENV_IS_IN_EEPROM
-#undef CFG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_EEPROM
+#elif defined CONFIG_ENV_IS_IN_EEPROM
+#undef CONFIG_ENV_IS_IN_NVRAM
 #undef CFG_ENV_IS_IN_FLASH
 #endif
 
@@ -243,12 +245,12 @@
 
 /* SDRAM configuration (for SPD) */
 #define CFG_SDRAM_TOTAL_BANKS		1
-#define CFG_SDRAM_SPD_I2C_ADDR		0x50  		/* 7bit */
+#define CFG_SDRAM_SPD_I2C_ADDR		0x50		/* 7bit */
 #define CFG_SDRAM_SPD_SIZE		0x100
-#define CFG_SDRAM_CAS_LATENCY		5 		/* (CL=2.5)x2 */
+#define CFG_SDRAM_CAS_LATENCY		5		/* (CL=2.5)x2 */
 
 /* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CFG_SDRAM_DRIVE_STRENGTH 	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
@@ -285,7 +287,7 @@
 
 #define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5   	/* log base 2 of the above value */
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*