X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsocfpga_common.h;h=cece0950e29769608f95730eed34f64657deb883;hb=a726075911c231e81ecbe12825840b6183bc10da;hp=afe363c5368e40fd66d3129e0f34f6f84e90c09e;hpb=a6e7359181637f8186d1c1fe7acb442a263e8c40;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index afe363c..cece095 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -13,18 +13,18 @@ #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SOCFPGA - /* * High level configuration */ #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS +#define CONFIG_CRC32_VERIFY + #define CONFIG_FIT #define CONFIG_OF_LIBFDT #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) @@ -41,10 +41,11 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET @@ -72,19 +73,22 @@ /* * Cache */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * SDRAM controller + */ +#define CONFIG_ALTERA_SDRAM + +/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR /* @@ -100,8 +104,6 @@ * Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define CONFIG_DESIGNWARE_ETH -#define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) @@ -139,7 +141,7 @@ #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 #endif /* @@ -189,17 +191,17 @@ unsigned int cm_get_l4_sp_clk_hz(void); /* * QSPI support */ -#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ -#define CONFIG_CMD_DM -#define CONFIG_DM -#define CONFIG_DM_SPI -#define CONFIG_DM_SPI_FLASH #define CONFIG_CADENCE_QSPI /* Enable multiple SPI NOR flash manufacturers */ -#define CONFIG_SPI_FLASH /* SPI flash subsystem */ #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SPI_FLASH_MTD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi" +#endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); @@ -207,19 +209,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CMD_SF -#endif +#define CONFIG_SPI_FLASH_BAR -#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ -#define CONFIG_CMD_DM -#define CONFIG_DM -#define CONFIG_DM_SPI +/* + * Designware SPI support + */ #define CONFIG_DESIGNWARE_SPI -#ifndef __ASSEMBLY__ -unsigned int cm_get_spi_controller_clk_hz(void); -#define CONFIG_DW_SPI_REF_CLK cm_get_spi_controller_clk_hz() -#endif #define CONFIG_CMD_SPI -#endif /* * Serial Driver @@ -261,10 +257,10 @@ unsigned int cm_get_spi_controller_clk_hz(void); #define CONFIG_USB_GADGET_VBUS_DRAW 2 /* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET -#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_DFU_FUNCTION +#define CONFIG_USB_FUNCTION_DFU #define CONFIG_DFU_MMC #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -285,7 +281,6 @@ unsigned int cm_get_spi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 4096 /* @@ -300,25 +295,44 @@ unsigned int cm_get_spi_controller_clk_hz(void); * 0xFFFF_FF00 ...... End of SRAM */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) - -#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT + +/* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_MMC_SUPPORT +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#define CONFIG_SPL_LIBDISK_SUPPORT +#else +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#endif +#endif -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +/* SPL QSPI boot support */ +#ifdef CONFIG_SPL_SPI_SUPPORT +#define CONFIG_DM_SEQ_ALIAS 1 +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif +/* + * Stack setup + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */