X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsocfpga_common.h;h=ce5781b806524f1cd7027cb560c15e14d39b3fff;hb=067716bac59716b07f1ee70d9bf6e5528289bb45;hp=b0bc68952ce408764793f87c5f47690647e028e2;hpb=123b70177931a5aed92beca76bb622b2f4005be8;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b0bc689..ce5781b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -3,9 +3,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ - +#ifndef __CONFIG_SOCFPGA_COMMON_H__ +#define __CONFIG_SOCFPGA_COMMON_H__ /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET @@ -24,12 +23,13 @@ #define CONFIG_CRC32_VERIFY -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" + /* * Memory configurations */ @@ -67,12 +67,14 @@ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ #define CONFIG_AUTO_COMPLETE /* Command auto complete */ #define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER + +#ifndef CONFIG_SYS_HOSTNAME +#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD +#endif /* * Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS @@ -85,10 +87,7 @@ * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_BAR /* * The base address is configurable in QSys, each board must specify the * base address based on it's particular FPGA configuration. Please note @@ -105,7 +104,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE #endif @@ -158,10 +156,22 @@ #endif /* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS +#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) +#endif + +/* * I2C support */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DW #define CONFIG_SYS_I2C_BUS_MAX 4 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS @@ -182,7 +192,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) #endif -#define CONFIG_CMD_I2C /* * QSPI support @@ -193,7 +202,7 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nor0=ff705000.spi" +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" #endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ @@ -201,13 +210,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_BAR /* * Designware SPI support */ -#define CONFIG_CMD_SPI /* * Serial Driver @@ -229,41 +235,24 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2 #define CONFIG_USB_STORAGE -/* - * NOTE: User must define either of the following to select which - * of the two USB controllers available on SoCFPGA to use. - * The DWC2 driver doesn't support multiple USB controllers. - * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS - * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS - */ #endif /* * USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_DWC2_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_FUNCTION_DFU +#ifdef CONFIG_DM_MMC #define CONFIG_DFU_MMC +#endif #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ -#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM -#ifndef CONFIG_G_DNL_MANUFACTURER -#define CONFIG_G_DNL_MANUFACTURER "Altera" -#endif +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #endif /* @@ -272,7 +261,52 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#if !defined(CONFIG_ENV_SIZE) #define CONFIG_ENV_SIZE 4096 +#endif + +/* Environment for SDMMC boot */ +#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ +#endif + +/* Environment for QSPI boot */ +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0x00100000 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#endif + +/* + * mtd partitioning for serial NOR flash + * + * device nor0 , # parts = 6 + * #: name size offset mask_flags + * 0: u-boot 0x00100000 0x00000000 0 + * 1: env1 0x00040000 0x00100000 0 + * 2: env2 0x00040000 0x00140000 0 + * 3: UBI 0x03e80000 0x00180000 0 + * 4: boot 0x00e80000 0x00180000 0 + * 5: rootfs 0x01000000 0x01000000 0 + * + */ +#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) +#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ + "1m(u-boot)," \ + "256k(env1)," \ + "256k(env2)," \ + "14848k(boot)," \ + "16m(rootfs)," \ + "-@1536k(UBI)\0" +#endif + +/* UBI and UBIFS support */ +#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif /* * SPL @@ -289,16 +323,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE (64 * 1024) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_DM_MMC #define CONFIG_SPL_MMC_SUPPORT +#endif +#ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT +#endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -307,23 +345,29 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */ +#define CONFIG_SPL_LIBDISK_SUPPORT #endif #endif /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT -#define CONFIG_DM_SEQ_ALIAS 1 #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif +/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif + /* * Stack setup */ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ +#endif /* __CONFIG_SOCFPGA_COMMON_H__ */