X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsocfpga_common.h;h=ce5781b806524f1cd7027cb560c15e14d39b3fff;hb=067716bac59716b07f1ee70d9bf6e5528289bb45;hp=56d32e6b53255c7fcf34057fb5a374df4c2436b2;hpb=83d95b67d3731e39292d858924ade3be68c167af;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 56d32e6..ce5781b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_SOCFPGA_COMMON_H__ #define __CONFIG_SOCFPGA_COMMON_H__ - /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET @@ -68,7 +67,6 @@ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ #define CONFIG_AUTO_COMPLETE /* Command auto complete */ #define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER #ifndef CONFIG_SYS_HOSTNAME #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD @@ -77,7 +75,6 @@ /* * Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS @@ -90,10 +87,7 @@ * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_BAR /* * The base address is configurable in QSys, each board must specify the * base address based on it's particular FPGA configuration. Please note @@ -178,7 +172,6 @@ * I2C support */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DW #define CONFIG_SYS_I2C_BUS_MAX 4 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS @@ -199,7 +192,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) #endif -#define CONFIG_CMD_I2C /* * QSPI support @@ -218,13 +210,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_BAR /* * Designware SPI support */ -#define CONFIG_CMD_SPI /* * Serial Driver @@ -252,13 +241,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_DWC2_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_FUNCTION_DFU @@ -269,13 +251,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ -#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM -#ifndef CONFIG_G_DNL_MANUFACTURER -#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR -#endif +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #endif /* @@ -346,9 +323,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE (64 * 1024) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -371,9 +345,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */ +#define CONFIG_SPL_LIBDISK_SUPPORT #endif #endif