X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsmartweb.h;h=75a1670e3317571de951f155bdec968114a64916;hb=HEAD;hp=65bc3c672eedef7513e16b818a064a8c1034d6d1;hpb=cd6a45a41fb2c19884ac87afade87b4d53601929;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 65bc3c6..75a1670 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -30,14 +30,14 @@
 #include <linux/sizes.h>
 
 /*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
+ * Warning: changing CONFIG_TEXT_BASE requires adapting the initial boot
  * program. Since the linker has to swallow that define, we must use a pure
  * hex number here!
  */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
 
 /* misc settings */
 
@@ -45,8 +45,8 @@
  * SDRAM: 1 bank, 64 MB, base address 0x20000000
  * Already initialized before u-boot gets started.
  */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		(64 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		(64 * SZ_1M)
 
 /*
  * Perform a SDRAM Memtest from the start of SDRAM
@@ -54,24 +54,15 @@
  */
 
 /* NAND flash settings */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 
 /* serial console */
-#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
-#define CONFIG_USART_ID			ATMEL_ID_SYS
-
-/* USB configuration */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
-
-/* USB DFU support */
-
-#define CONFIG_USB_GADGET_AT91
+#define CFG_USART_BASE		ATMEL_BASE_DBGU
+#define CFG_USART_ID			ATMEL_ID_SYS
 
 /* DFU class support */
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
@@ -82,7 +73,7 @@
  * Predefined environment variables.
  * Usefull to define some easy to use boot commands.
  */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define	CFG_EXTRA_ENV_SETTINGS					\
 									\
 	"basicargs=console=ttyS0,115200\0"				\
 									\
@@ -92,28 +83,26 @@
  * leaving the correct space for initial global data structure above that
  * address while providing maximum stack area below.
  */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_SIZE		(SZ_256M)
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
-#define CONFIG_SYS_MASTER_CLOCK		(198656000/2)
+#define CFG_SYS_MASTER_CLOCK		(198656000/2)
 #define AT91_PLL_LOCK_TIMEOUT		1000000
-#define CONFIG_SYS_AT91_PLLA		0x2060bf09
-#define CONFIG_SYS_MCKR			0x100
-#define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB		0x10483f0e
+#define CFG_SYS_AT91_PLLA		0x2060bf09
+#define CFG_SYS_MCKR			0x100
+#define CFG_SYS_MCKR_CSS		(0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB		0x10483f0e
 
 #endif /* __CONFIG_H */