X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsh7757lcr.h;h=ac6338cec1c72ef453c98a0f62e981a4ff84711c;hb=5fdb3c0e7ee6bac6b8809ae69e52f16d22d45035;hp=8ec4cd4430654da8d5a6b32d0c5b9f8b400ad507;hpb=f0ca30fa19ee57e2f8452a1d0b8a30eb923d7e22;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 8ec4cd4..ac6338c 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -1,26 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Configuation settings for the sh7757lcr board
  *
  * Copyright (C) 2011 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __SH7757LCR_H
 #define __SH7757LCR_H
 
 #define CONFIG_CPU_SH7757	1
-#define CONFIG_SH7757LCR	1
 #define CONFIG_SH7757LCR_DDR_ECC	1
 
-#define CONFIG_SYS_TEXT_BASE	0x8ef80000
-
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-
 #define CONFIG_DISPLAY_BOARDINFO
-#undef	CONFIG_SHOW_BOOT_PROGRESS
 
 /* MEMORY */
 #define SH7757LCR_SDRAM_BASE		(0x80000000)
@@ -28,21 +19,12 @@
 #define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
 #define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
 
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		512
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 
 /* SCIF */
 #define CONFIG_CONS_SCIF2	1
 
-#define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
-					 224 * 1024 * 1024)
-#undef	CONFIG_SYS_ALT_MEMTEST
-#undef	CONFIG_SYS_MEMTEST_SCRATCH
 #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
 
 #define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
@@ -56,11 +38,9 @@
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /* Ether */
-#define CONFIG_SH_ETHER			1
 #define CONFIG_SH_ETHER_USE_PORT	0
 #define CONFIG_SH_ETHER_PHY_ADDR	1
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
@@ -74,11 +54,9 @@
 #define SH7757LCR_GIGA_ETHERNET_NUM_CH	2
 
 /* SPI */
-#define CONFIG_SH_SPI			1
 #define CONFIG_SH_SPI_BASE		0xfe002000
 
 /* MMCIF */
-#define CONFIG_SH_MMCIF			1
 #define CONFIG_SH_MMCIF_ADDR		0xffcb0000
 #define CONFIG_SH_MMCIF_CLK		48000000
 
@@ -91,19 +69,11 @@
 #define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)
 
 /* ENV setting */
-#define CONFIG_ENV_IS_EMBEDDED
-#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
-#define CONFIG_ENV_ADDR		(0x00080000)
-#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
 #define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 		"netboot=bootp; bootm\0"
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV	4
 #endif	/* __SH7757LCR_H */