X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsc3.h;h=2a166bc416acbd95fbe7cfb6e28ee6314dfdeb7f;hb=553f09823cced77296825f615f00321d932bf914;hp=515b09789e73ca297113a6a9dc8ef4bafbefd336;hpb=5df70e91c72dab45b7d81e4568b12e5a5b5f90ec;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 515b097..2a166bc 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -62,7 +62,10 @@ #define CONFIG_4xx 1 #define CONFIG_405GP 1 +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 + #define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ /* * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range @@ -75,15 +78,12 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SERIAL_MULTI -#undef CONFIG_SERIAL_SOFTWARE_FIFO -/* - * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input - * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature - */ -#if CONFIG_SERIAL_SOFTWARE_FIFO - #define CONFIG_POWER_DOWN -#endif /* * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz @@ -122,7 +122,7 @@ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/sc3/uImage\0" \ "u-boot=/tftpboot/sc3/u-boot.bin\0" \ - "setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0" \ + "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \ "kernel_addr=FFE08000\0" \ "" #undef CONFIG_BOOTCOMMAND @@ -186,20 +186,20 @@ #include -#define CONFIG_CMD_AUTOSCRIPT -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE +#define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_CACHE #define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SOURCE #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -250,6 +250,7 @@ */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define I2C_INIT #define I2C_ACTIVE 0 @@ -375,15 +376,11 @@ * CONFIG_SYS_FLASH_BASE -> start address of internal flash * CONFIG_SYS_MONITOR_BASE -> start of u-boot */ -#ifndef __ASSEMBLER__ -extern unsigned long offsetOfBigFlash; -extern unsigned long offsetOfEnvironment; -#endif - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFFE00000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ -#define CONFIG_SYS_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ +#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ /* @@ -426,11 +423,10 @@ extern unsigned long offsetOfEnvironment; #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x77D00000 - #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ /* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nand0" #define CONFIG_JFFS2_PART_SIZE 0x01000000 #define CONFIG_JFFS2_PART_OFFSET 0x00000000 @@ -460,14 +456,14 @@ extern unsigned long offsetOfEnvironment; * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR * - Stackpointer will be located to * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) - * in cpu/ppc4xx/start.S + * in arch/powerpc/cpu/ppc4xx/start.S */ #undef CONFIG_SYS_INIT_DCACHE_CS /* Where the internal SRAM starts */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* Where the internal SRAM ends (only offset) */ -#define CONFIG_SYS_INIT_RAM_END 0x0F00 +#define CONFIG_SYS_INIT_RAM_SIZE 0x0F00 /* @@ -480,26 +476,18 @@ extern unsigned long offsetOfEnvironment; | | | 64 Bytes | | | - CONFIG_SYS_INIT_RAM_END ------> ------------ higher address + CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address (offset only) */ /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 64 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) /* Initial value of the stack pointern in internal SRAM */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - /* ################################################################################### */ -/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */ +/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ /* This chip select accesses the boot device */